Max Köhler
e9700b2081
So far only the implementation after opt_run is affected by the changes. Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
62 lines
2.7 KiB
Makefile
62 lines
2.7 KiB
Makefile
#
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# Copyright 2014-2015 Ettus Research
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#
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include $(BASE_DIR)/../tools/make/viv_preamble.mak
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SIMULATION = 0
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# -------------------------------------------------------------------
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# Usage: BUILD_VIVADO_DESIGN
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# Args: $1 = TCL_SCRIPT_NAME
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# $2 = TOP_MODULE
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# $3 = ARCH (zynq, kintex7, etc)
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# $4 = PART_ID (<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]])
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# Prereqs:
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# - TOOLS_DIR must be defined globally
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# - BUILD_DIR must be defined globally
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# - DESIGN_SRCS must be defined and should contain all source files
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# - VERILOG_DEFS must be defined and should contain all PP defines
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# - INCR_BUILD can be defined and runs parts of the Vivado flow in incremental mode
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# -------------------------------------------------------------------
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BUILD_VIVADO_DESIGN = \
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@ \
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export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
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export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
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export VIV_TOP_MODULE=$(2); \
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export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
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export VIV_MODE=$(VIVADO_MODE); \
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export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
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export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
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export VIV_INCR_BUILD=$(INCR_BUILD); \
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cd $(BUILD_DIR); \
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$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
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# -------------------------------------------------------------------
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# Usage: CHECK_VIVADO_DESIGN
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# Args: $1 = TCL_SCRIPT_NAME
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# $2 = TOP_MODULE
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# $3 = ARCH (zynq, kintex7, etc)
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# $4 = PART_ID (<device>/<package>/<speedgrade>[/<temperaturegrade>[/<silicon_revision>]])
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# Prereqs:
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# - TOOLS_DIR must be defined globally
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# - BUILD_DIR must be defined globally
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# - DESIGN_SRCS must be defined and should contain all source files
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# - VERILOG_DEFS must be defined and should contain all PP defines
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# -------------------------------------------------------------------
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CHECK_VIVADO_DESIGN = \
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@ \
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export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \
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export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \
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export VIV_TOP_MODULE=$(2); \
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export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
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export VIV_MODE=$(VIVADO_MODE); \
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export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
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export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
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cd $(BUILD_DIR); \
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$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
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# Predeclare RFNOC_OOT_SRCS to make sure it's not recursively expanded
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RFNOC_OOT_SRCS :=
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