fpga: x4xx: add option for incremental Vivado build

So far only the implementation after opt_run is affected by the changes.


Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6

tools/make/viv_design_builder.mak

@@ -16,6 +16,7 @@ SIMULATION = 0
 # - BUILD_DIR must be defined globally
 # - DESIGN_SRCS must be defined and should contain all source files
 # - VERILOG_DEFS must be defined and should contain all PP defines
+# - INCR_BUILD can be defined and runs parts of the Vivado flow in incremental mode
 # -------------------------------------------------------------------
 BUILD_VIVADO_DESIGN = \
 	@ \
@@ -26,6 +27,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
+	export VIV_INCR_BUILD=$(INCR_BUILD); \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
 

tools/scripts/viv_strategies.tcl

@@ -13,18 +13,18 @@ namespace eval ::vivado_strategies {
         check_strategy \
         print_strategy
 
-    variable g_viv_version [version -short]
+    # Required environment variables
+    variable g_output_dir  $::env(VIV_OUTPUT_DIR)
 }
 
 # ---------------------------------------------------
 # Return a preset strategy with the most commonly used options
 # ---------------------------------------------------
 proc ::vivado_strategies::get_impl_preset {preset} {
-    variable g_viv_version
-
     set strategy [dict create]
     switch -nocase $preset {
         "Default" {
+            dict set strategy "implementation.incremental"              0
             dict set strategy "opt_design.is_enabled"                   1
             dict set strategy "opt_design.directive"                    "Default"
             dict set strategy "post_opt_power_opt_design.is_enabled"    0
@@ -38,6 +38,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
             dict set strategy "post_route_phys_opt_design.directive"    "Default"
         }
         "Performance_Explore" {
+            dict set strategy "implementation.incremental"              0
             dict set strategy "opt_design.is_enabled"                   1
             dict set strategy "opt_design.directive"                    "Explore"
             dict set strategy "post_opt_power_opt_design.is_enabled"    0
@@ -51,6 +52,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
             dict set strategy "post_route_phys_opt_design.directive"    "Explore"
         }
         "Performance_ExplorePostRoutePhysOpt" {
+            dict set strategy "implementation.incremental"              0
             dict set strategy "opt_design.is_enabled"                   1
             dict set strategy "opt_design.directive"                    "Explore"
             dict set strategy "post_opt_power_opt_design.is_enabled"    0
@@ -71,7 +73,7 @@ proc ::vivado_strategies::get_impl_preset {preset} {
 # Execute the specified implementation strategy
 # ---------------------------------------------------
 proc ::vivado_strategies::implement_design {strategy} {
-    variable g_viv_version
+    variable g_output_dir
 
     # Check strategy for validity and print
     vivado_strategies::check_strategy $strategy
@@ -85,6 +87,17 @@ proc ::vivado_strategies::implement_design {strategy} {
         opt_design -directive $opt_dir
     }
 
+    # Reading former post-route checkpoint for incremental implementation.
+    # This will set all consecutive operations into incremental operation mode in case there
+    # is a post_route checkpoint from a previous run.
+    if [dict get $strategy "implementation.incremental"] {
+        set impl_checkpoint $g_output_dir/post_route.dcp
+        if {[file exists $impl_checkpoint]} {
+            # read incremental checkpoint
+            read_checkpoint -incremental $impl_checkpoint
+        }
+    }
+
     # Optimize dynamic power using intelligent clock gating after optimization
     if [dict get $strategy "post_opt_power_opt_design.is_enabled"] {
         power_opt_design
@@ -133,10 +146,9 @@ proc ::vivado_strategies::implement_design {strategy} {
 # Sanity-check the specified strategy
 # ---------------------------------------------------
 proc ::vivado_strategies::check_strategy {strategy} {
-    variable g_viv_version
-
     set strategy_options [dict keys $strategy]
     set required_options {\
+        implementation.incremental \
         opt_design.is_enabled \
         opt_design.directive \
         post_opt_power_opt_design.is_enabled \
@@ -165,8 +177,6 @@ proc ::vivado_strategies::check_strategy {strategy} {
 # Print strategy parameters to the console
 # ---------------------------------------------------
 proc ::vivado_strategies::print_strategy {strategy} {
-    variable g_viv_version
-
     foreach opt [dict keys $strategy] {
         set val [dict get $strategy $opt]
         puts "         * $opt = $val"

top/x400/Makefile

@@ -82,6 +82,9 @@ DEFS += $(OPTIONS)
 BUILD_SEED ?= 0
 DEFS += BUILD_SEED=$(BUILD_SEED)
 
+# Default value for incremental Vivado build is disabled. 
+INCR_BUILD ?= 0
+
 # Defaults specific to the various targets:
 X410_200_DEFAULTS     := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v     DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
 X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
@@ -107,7 +110,7 @@ endif
 TOP ?= x4xx
 
 # vivado_build($1=Device, $2=Definitions, $3=Defaults)
-vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
+vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 INCR_BUILD=$(INCR_BUILD)
 vivado_ip    = make -f Makefile.x4xx.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
 
 # vivado_build($1=Device, $2=Option)
@@ -325,6 +328,7 @@ help:         ##Show this help message.
 ##
 ##Supported Options
 ##-----------------
+##INCR_BUILD=0   Use incremental Vivado build to speed up consecutive runs
 ##DRAM=0         Exclude DDR4 memory controller IP from the FPGA build.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.

top/x400/build_x4xx.tcl

@@ -11,17 +11,17 @@ source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
 vivado_utils::initialize_project
 
 # STEP#2: Run synthesis
-
-
 vivado_utils::synthesize_design
 vivado_utils::generate_post_synth_reports
 
 # STEP#3: Run implementation strategy
 set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
+# Enable incremental build
+dict set strategy "implementation.incremental" $::env(VIV_INCR_BUILD)
 # Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
 set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
 # Vivado has been underestimating routing delays.
-dict set strategy "place_design.directive"                  "ExtraNetDelay_high"
+dict set strategy "place_design.directive" "ExtraNetDelay_high"
 # Turn down uncertainty on 100Gb clocks
 dict set strategy "route_design.pre_hook" {set_clock_uncertainty 0.0 -quiet -setup [get_clocks txoutclk_out*]}
 vivado_strategies::implement_design $strategy