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fpga: x4xx: add option for incremental Vivado build

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So far only the implementation after opt_run is affected by the changes.


Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
This commit is contained in:
Max Köhler
2024-03-12 16:03:23 -05:00
committed by Wade Fife
parent 275373c06b
commit e9700b2081
4 changed files with 28 additions and 12 deletions
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tools/make/viv_design_builder.mak
+2
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@@ -16,6 +16,7 @@ SIMULATION = 0
# - BUILD_DIR must be defined globally
# - DESIGN_SRCS must be defined and should contain all source files
# - VERILOG_DEFS must be defined and should contain all PP defines
# - INCR_BUILD can be defined and runs parts of the Vivado flow in incremental mode
# -------------------------------------------------------------------
BUILD_VIVADO_DESIGN = \
@ \
@@ -26,6 +27,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_MODE=$(VIVADO_MODE); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
export VIV_INCR_BUILD=$(INCR_BUILD); \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou