fpga: x400: Split DRAM interface into two banks
This updates the RFNoC image cores to separate the two DRAM banks on X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM banks shared the same DRAM port, named "dram", which created some confusion. The Replay block has also been duplicated in the bitstreams that use both banks, so we now have one Replay block per bank. Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
This commit is contained in:
Wade Fife
+28
-28
@@ -43,34 +43,34 @@ QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disa
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# Target specific variables
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# Target specific variables
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X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
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X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
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X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=0
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=0
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_CH=0
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X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
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X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
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X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# exclude it. Note that some targets exclude it regardless of this setting.
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# exclude it. Note that some targets exclude it regardless of this setting.
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@@ -36,10 +36,10 @@ module rfnoc_image_core #(
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input wire chdr_aclk,
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire core_arst,
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input wire ce_clk,
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input wire radio_clk,
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input wire radio_clk,
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input wire radio_2x_clk,
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input wire radio_2x_clk,
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input wire dram_clk,
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input wire dram_clk,
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input wire ce_clk,
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// Basic
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// Basic
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input wire [ 15:0] device_id,
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input wire [ 15:0] device_id,
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@@ -83,52 +83,98 @@ module rfnoc_image_core #(
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output wire [1023:0] radio_tx_data_radio1,
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output wire [1023:0] radio_tx_data_radio1,
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input wire [ 31:0] radio_tx_stb_radio1,
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input wire [ 31:0] radio_tx_stb_radio1,
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output wire [ 31:0] radio_tx_running_radio1,
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output wire [ 31:0] radio_tx_running_radio1,
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// dram
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// dram0
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input wire [ 0:0] axi_rst,
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input wire [ 0:0] dram0_axi_rst,
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output wire [ 7:0] m_axi_awid,
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output wire [ 7:0] dram0_m_axi_awid,
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output wire [ 383:0] m_axi_awaddr,
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output wire [ 383:0] dram0_m_axi_awaddr,
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output wire [ 63:0] m_axi_awlen,
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output wire [ 63:0] dram0_m_axi_awlen,
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output wire [ 23:0] m_axi_awsize,
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output wire [ 23:0] dram0_m_axi_awsize,
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output wire [ 15:0] m_axi_awburst,
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output wire [ 15:0] dram0_m_axi_awburst,
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output wire [ 7:0] m_axi_awlock,
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output wire [ 7:0] dram0_m_axi_awlock,
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output wire [ 31:0] m_axi_awcache,
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output wire [ 31:0] dram0_m_axi_awcache,
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output wire [ 23:0] m_axi_awprot,
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output wire [ 23:0] dram0_m_axi_awprot,
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output wire [ 31:0] m_axi_awqos,
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output wire [ 31:0] dram0_m_axi_awqos,
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output wire [ 31:0] m_axi_awregion,
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output wire [ 31:0] dram0_m_axi_awregion,
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output wire [ 7:0] m_axi_awuser,
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output wire [ 7:0] dram0_m_axi_awuser,
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output wire [ 7:0] m_axi_awvalid,
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output wire [ 7:0] dram0_m_axi_awvalid,
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input wire [ 7:0] m_axi_awready,
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input wire [ 7:0] dram0_m_axi_awready,
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output wire [4191:0] m_axi_wdata,
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output wire [4191:0] dram0_m_axi_wdata,
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output wire [ 511:0] m_axi_wstrb,
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output wire [ 511:0] dram0_m_axi_wstrb,
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output wire [ 7:0] m_axi_wlast,
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output wire [ 7:0] dram0_m_axi_wlast,
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output wire [ 7:0] m_axi_wuser,
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output wire [ 7:0] dram0_m_axi_wuser,
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output wire [ 7:0] m_axi_wvalid,
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output wire [ 7:0] dram0_m_axi_wvalid,
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input wire [ 7:0] m_axi_wready,
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input wire [ 7:0] dram0_m_axi_wready,
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input wire [ 7:0] m_axi_bid,
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input wire [ 7:0] dram0_m_axi_bid,
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input wire [ 15:0] m_axi_bresp,
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input wire [ 15:0] dram0_m_axi_bresp,
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input wire [ 7:0] m_axi_buser,
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input wire [ 7:0] dram0_m_axi_buser,
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input wire [ 7:0] m_axi_bvalid,
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input wire [ 7:0] dram0_m_axi_bvalid,
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output wire [ 7:0] m_axi_bready,
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output wire [ 7:0] dram0_m_axi_bready,
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output wire [ 7:0] m_axi_arid,
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output wire [ 7:0] dram0_m_axi_arid,
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output wire [ 383:0] m_axi_araddr,
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output wire [ 383:0] dram0_m_axi_araddr,
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output wire [ 63:0] m_axi_arlen,
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output wire [ 63:0] dram0_m_axi_arlen,
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output wire [ 23:0] m_axi_arsize,
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output wire [ 23:0] dram0_m_axi_arsize,
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output wire [ 15:0] m_axi_arburst,
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output wire [ 15:0] dram0_m_axi_arburst,
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output wire [ 7:0] m_axi_arlock,
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output wire [ 7:0] dram0_m_axi_arlock,
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output wire [ 31:0] m_axi_arcache,
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output wire [ 31:0] dram0_m_axi_arcache,
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output wire [ 31:0] m_axi_arprot,
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output wire [ 31:0] dram0_m_axi_arprot,
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output wire [ 31:0] m_axi_arqos,
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output wire [ 31:0] dram0_m_axi_arqos,
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output wire [ 31:0] m_axi_arregion,
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output wire [ 31:0] dram0_m_axi_arregion,
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output wire [ 7:0] m_axi_aruser,
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output wire [ 7:0] dram0_m_axi_aruser,
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output wire [ 7:0] m_axi_arvalid,
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output wire [ 7:0] dram0_m_axi_arvalid,
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input wire [ 7:0] m_axi_arready,
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input wire [ 7:0] dram0_m_axi_arready,
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input wire [ 7:0] m_axi_rid,
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input wire [ 7:0] dram0_m_axi_rid,
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input wire [4191:0] m_axi_rdata,
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input wire [4191:0] dram0_m_axi_rdata,
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input wire [ 15:0] m_axi_rresp,
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input wire [ 15:0] dram0_m_axi_rresp,
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input wire [ 7:0] m_axi_rlast,
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input wire [ 7:0] dram0_m_axi_rlast,
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input wire [ 7:0] m_axi_ruser,
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input wire [ 7:0] dram0_m_axi_ruser,
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input wire [ 7:0] m_axi_rvalid,
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input wire [ 7:0] dram0_m_axi_rvalid,
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output wire [ 7:0] m_axi_rready,
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output wire [ 7:0] dram0_m_axi_rready,
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// dram1
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input wire [ 0:0] dram1_axi_rst,
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output wire [ 7:0] dram1_m_axi_awid,
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output wire [ 383:0] dram1_m_axi_awaddr,
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output wire [ 63:0] dram1_m_axi_awlen,
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output wire [ 23:0] dram1_m_axi_awsize,
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output wire [ 15:0] dram1_m_axi_awburst,
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output wire [ 7:0] dram1_m_axi_awlock,
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output wire [ 31:0] dram1_m_axi_awcache,
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output wire [ 23:0] dram1_m_axi_awprot,
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output wire [ 31:0] dram1_m_axi_awqos,
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output wire [ 31:0] dram1_m_axi_awregion,
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output wire [ 7:0] dram1_m_axi_awuser,
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output wire [ 7:0] dram1_m_axi_awvalid,
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input wire [ 7:0] dram1_m_axi_awready,
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output wire [4191:0] dram1_m_axi_wdata,
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output wire [ 511:0] dram1_m_axi_wstrb,
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output wire [ 7:0] dram1_m_axi_wlast,
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output wire [ 7:0] dram1_m_axi_wuser,
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output wire [ 7:0] dram1_m_axi_wvalid,
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input wire [ 7:0] dram1_m_axi_wready,
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input wire [ 7:0] dram1_m_axi_bid,
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input wire [ 15:0] dram1_m_axi_bresp,
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input wire [ 7:0] dram1_m_axi_buser,
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input wire [ 7:0] dram1_m_axi_bvalid,
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output wire [ 7:0] dram1_m_axi_bready,
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output wire [ 7:0] dram1_m_axi_arid,
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output wire [ 383:0] dram1_m_axi_araddr,
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output wire [ 63:0] dram1_m_axi_arlen,
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output wire [ 23:0] dram1_m_axi_arsize,
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output wire [ 15:0] dram1_m_axi_arburst,
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output wire [ 7:0] dram1_m_axi_arlock,
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output wire [ 31:0] dram1_m_axi_arcache,
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output wire [ 31:0] dram1_m_axi_arprot,
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output wire [ 31:0] dram1_m_axi_arqos,
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output wire [ 31:0] dram1_m_axi_arregion,
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output wire [ 7:0] dram1_m_axi_aruser,
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output wire [ 7:0] dram1_m_axi_arvalid,
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input wire [ 7:0] dram1_m_axi_arready,
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input wire [ 7:0] dram1_m_axi_rid,
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input wire [4191:0] dram1_m_axi_rdata,
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input wire [ 15:0] dram1_m_axi_rresp,
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input wire [ 7:0] dram1_m_axi_rlast,
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input wire [ 7:0] dram1_m_axi_ruser,
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input wire [ 7:0] dram1_m_axi_rvalid,
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output wire [ 7:0] dram1_m_axi_rready,
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// Transport Adapters ///////////////
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// Transport Adapters ///////////////
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@@ -1664,51 +1710,51 @@ module rfnoc_image_core #(
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assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
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assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
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assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
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assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
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assign replay0_axi_rst = axi_rst;
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assign replay0_axi_rst = dram0_axi_rst;
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assign m_axi_awid = replay0_m_axi_awid;
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assign dram0_m_axi_awid = replay0_m_axi_awid;
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assign m_axi_awaddr = replay0_m_axi_awaddr;
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assign dram0_m_axi_awaddr = replay0_m_axi_awaddr;
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||||||
assign m_axi_awlen = replay0_m_axi_awlen;
|
assign dram0_m_axi_awlen = replay0_m_axi_awlen;
|
||||||
assign m_axi_awsize = replay0_m_axi_awsize;
|
assign dram0_m_axi_awsize = replay0_m_axi_awsize;
|
||||||
assign m_axi_awburst = replay0_m_axi_awburst;
|
assign dram0_m_axi_awburst = replay0_m_axi_awburst;
|
||||||
assign m_axi_awlock = replay0_m_axi_awlock;
|
assign dram0_m_axi_awlock = replay0_m_axi_awlock;
|
||||||
assign m_axi_awcache = replay0_m_axi_awcache;
|
assign dram0_m_axi_awcache = replay0_m_axi_awcache;
|
||||||
assign m_axi_awprot = replay0_m_axi_awprot;
|
assign dram0_m_axi_awprot = replay0_m_axi_awprot;
|
||||||
assign m_axi_awqos = replay0_m_axi_awqos;
|
assign dram0_m_axi_awqos = replay0_m_axi_awqos;
|
||||||
assign m_axi_awregion = replay0_m_axi_awregion;
|
assign dram0_m_axi_awregion = replay0_m_axi_awregion;
|
||||||
assign m_axi_awuser = replay0_m_axi_awuser;
|
assign dram0_m_axi_awuser = replay0_m_axi_awuser;
|
||||||
assign m_axi_awvalid = replay0_m_axi_awvalid;
|
assign dram0_m_axi_awvalid = replay0_m_axi_awvalid;
|
||||||
assign replay0_m_axi_awready = m_axi_awready;
|
assign replay0_m_axi_awready = dram0_m_axi_awready;
|
||||||
assign m_axi_wdata = replay0_m_axi_wdata;
|
assign dram0_m_axi_wdata = replay0_m_axi_wdata;
|
||||||
assign m_axi_wstrb = replay0_m_axi_wstrb;
|
assign dram0_m_axi_wstrb = replay0_m_axi_wstrb;
|
||||||
assign m_axi_wlast = replay0_m_axi_wlast;
|
assign dram0_m_axi_wlast = replay0_m_axi_wlast;
|
||||||
assign m_axi_wuser = replay0_m_axi_wuser;
|
assign dram0_m_axi_wuser = replay0_m_axi_wuser;
|
||||||
assign m_axi_wvalid = replay0_m_axi_wvalid;
|
assign dram0_m_axi_wvalid = replay0_m_axi_wvalid;
|
||||||
assign replay0_m_axi_wready = m_axi_wready;
|
assign replay0_m_axi_wready = dram0_m_axi_wready;
|
||||||
assign replay0_m_axi_bid = m_axi_bid;
|
assign replay0_m_axi_bid = dram0_m_axi_bid;
|
||||||
assign replay0_m_axi_bresp = m_axi_bresp;
|
assign replay0_m_axi_bresp = dram0_m_axi_bresp;
|
||||||
assign replay0_m_axi_buser = m_axi_buser;
|
assign replay0_m_axi_buser = dram0_m_axi_buser;
|
||||||
assign replay0_m_axi_bvalid = m_axi_bvalid;
|
assign replay0_m_axi_bvalid = dram0_m_axi_bvalid;
|
||||||
assign m_axi_bready = replay0_m_axi_bready;
|
assign dram0_m_axi_bready = replay0_m_axi_bready;
|
||||||
assign m_axi_arid = replay0_m_axi_arid;
|
assign dram0_m_axi_arid = replay0_m_axi_arid;
|
||||||
assign m_axi_araddr = replay0_m_axi_araddr;
|
assign dram0_m_axi_araddr = replay0_m_axi_araddr;
|
||||||
assign m_axi_arlen = replay0_m_axi_arlen;
|
assign dram0_m_axi_arlen = replay0_m_axi_arlen;
|
||||||
assign m_axi_arsize = replay0_m_axi_arsize;
|
assign dram0_m_axi_arsize = replay0_m_axi_arsize;
|
||||||
assign m_axi_arburst = replay0_m_axi_arburst;
|
assign dram0_m_axi_arburst = replay0_m_axi_arburst;
|
||||||
assign m_axi_arlock = replay0_m_axi_arlock;
|
assign dram0_m_axi_arlock = replay0_m_axi_arlock;
|
||||||
assign m_axi_arcache = replay0_m_axi_arcache;
|
assign dram0_m_axi_arcache = replay0_m_axi_arcache;
|
||||||
assign m_axi_arprot = replay0_m_axi_arprot;
|
assign dram0_m_axi_arprot = replay0_m_axi_arprot;
|
||||||
assign m_axi_arqos = replay0_m_axi_arqos;
|
assign dram0_m_axi_arqos = replay0_m_axi_arqos;
|
||||||
assign m_axi_arregion = replay0_m_axi_arregion;
|
assign dram0_m_axi_arregion = replay0_m_axi_arregion;
|
||||||
assign m_axi_aruser = replay0_m_axi_aruser;
|
assign dram0_m_axi_aruser = replay0_m_axi_aruser;
|
||||||
assign m_axi_arvalid = replay0_m_axi_arvalid;
|
assign dram0_m_axi_arvalid = replay0_m_axi_arvalid;
|
||||||
assign replay0_m_axi_arready = m_axi_arready;
|
assign replay0_m_axi_arready = dram0_m_axi_arready;
|
||||||
assign replay0_m_axi_rid = m_axi_rid;
|
assign replay0_m_axi_rid = dram0_m_axi_rid;
|
||||||
assign replay0_m_axi_rdata = m_axi_rdata;
|
assign replay0_m_axi_rdata = dram0_m_axi_rdata;
|
||||||
assign replay0_m_axi_rresp = m_axi_rresp;
|
assign replay0_m_axi_rresp = dram0_m_axi_rresp;
|
||||||
assign replay0_m_axi_rlast = m_axi_rlast;
|
assign replay0_m_axi_rlast = dram0_m_axi_rlast;
|
||||||
assign replay0_m_axi_ruser = m_axi_ruser;
|
assign replay0_m_axi_ruser = dram0_m_axi_ruser;
|
||||||
assign replay0_m_axi_rvalid = m_axi_rvalid;
|
assign replay0_m_axi_rvalid = dram0_m_axi_rvalid;
|
||||||
assign m_axi_rready = replay0_m_axi_rready;
|
assign dram0_m_axi_rready = replay0_m_axi_rready;
|
||||||
|
|
||||||
assign radio0_radio_rx_data = radio_rx_data_radio0;
|
assign radio0_radio_rx_data = radio_rx_data_radio0;
|
||||||
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
|
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
|
||||||
|
|||||||
@@ -136,7 +136,7 @@ connections:
|
|||||||
# BSP Connections
|
# BSP Connections
|
||||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||||
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
||||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
|
||||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||||
|
|||||||
@@ -36,10 +36,10 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio_clk,
|
input wire radio_clk,
|
||||||
input wire radio_2x_clk,
|
input wire radio_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -83,52 +83,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
@@ -920,10 +966,14 @@ module rfnoc_image_core #(
|
|||||||
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
||||||
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
||||||
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
||||||
|
wire [31:0] m_replay1_ctrl_tdata, s_replay1_ctrl_tdata;
|
||||||
|
wire m_replay1_ctrl_tlast, s_replay1_ctrl_tlast;
|
||||||
|
wire m_replay1_ctrl_tvalid, s_replay1_ctrl_tvalid;
|
||||||
|
wire m_replay1_ctrl_tready, s_replay1_ctrl_tready;
|
||||||
|
|
||||||
axis_ctrl_crossbar_nxn #(
|
axis_ctrl_crossbar_nxn #(
|
||||||
.WIDTH (32),
|
.WIDTH (32),
|
||||||
.NPORTS (5),
|
.NPORTS (6),
|
||||||
.TOPOLOGY ("TORUS"),
|
.TOPOLOGY ("TORUS"),
|
||||||
.INGRESS_BUFF_SIZE(5),
|
.INGRESS_BUFF_SIZE(5),
|
||||||
.ROUTER_BUFF_SIZE (5),
|
.ROUTER_BUFF_SIZE (5),
|
||||||
@@ -932,14 +982,14 @@ module rfnoc_image_core #(
|
|||||||
) ctrl_xb_i (
|
) ctrl_xb_i (
|
||||||
.clk (rfnoc_ctrl_clk),
|
.clk (rfnoc_ctrl_clk),
|
||||||
.reset (rfnoc_ctrl_rst),
|
.reset (rfnoc_ctrl_rst),
|
||||||
.s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
.s_axis_tdata ({m_replay1_ctrl_tdata , m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
||||||
.s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
.s_axis_tvalid ({m_replay1_ctrl_tvalid, m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
||||||
.s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
.s_axis_tlast ({m_replay1_ctrl_tlast , m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
||||||
.s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
.s_axis_tready ({m_replay1_ctrl_tready, m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
||||||
.m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
.m_axis_tdata ({s_replay1_ctrl_tdata , s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
||||||
.m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
.m_axis_tvalid ({s_replay1_ctrl_tvalid, s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
||||||
.m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
.m_axis_tlast ({s_replay1_ctrl_tlast , s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
||||||
.m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
.m_axis_tready ({s_replay1_ctrl_tready, s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
||||||
.deadlock_detected()
|
.deadlock_detected()
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -948,14 +998,14 @@ module rfnoc_image_core #(
|
|||||||
// RFNoC Core Kernel
|
// RFNoC Core Kernel
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
|
wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
|
||||||
|
|
||||||
rfnoc_core_kernel #(
|
rfnoc_core_kernel #(
|
||||||
.PROTOVER (PROTOVER),
|
.PROTOVER (PROTOVER),
|
||||||
.DEVICE_TYPE (16'hA400),
|
.DEVICE_TYPE (16'hA400),
|
||||||
.DEVICE_FAMILY ("ULTRASCALE"),
|
.DEVICE_FAMILY ("ULTRASCALE"),
|
||||||
.SAFE_START_CLKS (0),
|
.SAFE_START_CLKS (0),
|
||||||
.NUM_BLOCKS (3),
|
.NUM_BLOCKS (4),
|
||||||
.NUM_STREAM_ENDPOINTS(8),
|
.NUM_STREAM_ENDPOINTS(8),
|
||||||
.NUM_ENDPOINTS_CTRL (1),
|
.NUM_ENDPOINTS_CTRL (1),
|
||||||
.NUM_TRANSPORTS (6),
|
.NUM_TRANSPORTS (6),
|
||||||
@@ -1165,14 +1215,14 @@ module rfnoc_image_core #(
|
|||||||
//-----------------------------------
|
//-----------------------------------
|
||||||
|
|
||||||
wire replay0_mem_clk;
|
wire replay0_mem_clk;
|
||||||
wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
|
||||||
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
|
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
|
||||||
wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
|
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
|
||||||
wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
|
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
|
||||||
wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
|
||||||
wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
|
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
|
||||||
wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
|
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
|
||||||
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
|
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
|
||||||
|
|
||||||
// axi_ram
|
// axi_ram
|
||||||
wire [ 0:0] replay0_axi_rst;
|
wire [ 0:0] replay0_axi_rst;
|
||||||
@@ -1224,7 +1274,7 @@ module rfnoc_image_core #(
|
|||||||
rfnoc_block_replay #(
|
rfnoc_block_replay #(
|
||||||
.THIS_PORTID (4),
|
.THIS_PORTID (4),
|
||||||
.CHDR_W (BLOCK_CHDR_W),
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
.NUM_PORTS (4),
|
.NUM_PORTS (2),
|
||||||
.MEM_DATA_W (128),
|
.MEM_DATA_W (128),
|
||||||
.MEM_ADDR_W (32),
|
.MEM_ADDR_W (32),
|
||||||
.MTU (BLOCK_MTU)
|
.MTU (BLOCK_MTU)
|
||||||
@@ -1279,14 +1329,14 @@ module rfnoc_image_core #(
|
|||||||
.m_axi_ruser (replay0_m_axi_ruser),
|
.m_axi_ruser (replay0_m_axi_ruser),
|
||||||
.m_axi_rvalid (replay0_m_axi_rvalid),
|
.m_axi_rvalid (replay0_m_axi_rvalid),
|
||||||
.m_axi_rready (replay0_m_axi_rready),
|
.m_axi_rready (replay0_m_axi_rready),
|
||||||
.s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
|
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
|
||||||
.s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
|
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
|
||||||
.s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
|
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
|
||||||
.s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
|
.s_rfnoc_chdr_tready ({s_replay0_in_1_tready, s_replay0_in_0_tready}),
|
||||||
.m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
|
.m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
|
||||||
.m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
|
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
|
||||||
.m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
|
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
|
||||||
.m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
|
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
|
||||||
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
||||||
@@ -1297,6 +1347,143 @@ module rfnoc_image_core #(
|
|||||||
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//-----------------------------------
|
||||||
|
// replay1
|
||||||
|
//-----------------------------------
|
||||||
|
|
||||||
|
wire replay1_mem_clk;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] s_replay1_in_1_tdata , s_replay1_in_0_tdata ;
|
||||||
|
wire s_replay1_in_1_tlast , s_replay1_in_0_tlast ;
|
||||||
|
wire s_replay1_in_1_tvalid, s_replay1_in_0_tvalid;
|
||||||
|
wire s_replay1_in_1_tready, s_replay1_in_0_tready;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] m_replay1_out_1_tdata , m_replay1_out_0_tdata ;
|
||||||
|
wire m_replay1_out_1_tlast , m_replay1_out_0_tlast ;
|
||||||
|
wire m_replay1_out_1_tvalid, m_replay1_out_0_tvalid;
|
||||||
|
wire m_replay1_out_1_tready, m_replay1_out_0_tready;
|
||||||
|
|
||||||
|
// axi_ram
|
||||||
|
wire [ 0:0] replay1_axi_rst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awid;
|
||||||
|
wire [ 383:0] replay1_m_axi_awaddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_awlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_awsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_awburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_awcache;
|
||||||
|
wire [ 23:0] replay1_m_axi_awprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_awqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_awregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_awuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_awvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_awready;
|
||||||
|
wire [4191:0] replay1_m_axi_wdata;
|
||||||
|
wire [ 511:0] replay1_m_axi_wstrb;
|
||||||
|
wire [ 7:0] replay1_m_axi_wlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_wuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_wvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_wready;
|
||||||
|
wire [ 7:0] replay1_m_axi_bid;
|
||||||
|
wire [ 15:0] replay1_m_axi_bresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_buser;
|
||||||
|
wire [ 7:0] replay1_m_axi_bvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_bready;
|
||||||
|
wire [ 7:0] replay1_m_axi_arid;
|
||||||
|
wire [ 383:0] replay1_m_axi_araddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_arlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_arsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_arburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_arlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_arcache;
|
||||||
|
wire [ 31:0] replay1_m_axi_arprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_arqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_arregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_aruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_arvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_arready;
|
||||||
|
wire [ 7:0] replay1_m_axi_rid;
|
||||||
|
wire [4191:0] replay1_m_axi_rdata;
|
||||||
|
wire [ 15:0] replay1_m_axi_rresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_rlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_ruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_rvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_rready;
|
||||||
|
|
||||||
|
rfnoc_block_replay #(
|
||||||
|
.THIS_PORTID (5),
|
||||||
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
|
.NUM_PORTS (2),
|
||||||
|
.MEM_DATA_W (128),
|
||||||
|
.MEM_ADDR_W (32),
|
||||||
|
.MTU (BLOCK_MTU)
|
||||||
|
) b_replay1_3 (
|
||||||
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.mem_clk (replay1_mem_clk),
|
||||||
|
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
|
||||||
|
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
|
||||||
|
.axi_rst (replay1_axi_rst),
|
||||||
|
.m_axi_awid (replay1_m_axi_awid),
|
||||||
|
.m_axi_awaddr (replay1_m_axi_awaddr),
|
||||||
|
.m_axi_awlen (replay1_m_axi_awlen),
|
||||||
|
.m_axi_awsize (replay1_m_axi_awsize),
|
||||||
|
.m_axi_awburst (replay1_m_axi_awburst),
|
||||||
|
.m_axi_awlock (replay1_m_axi_awlock),
|
||||||
|
.m_axi_awcache (replay1_m_axi_awcache),
|
||||||
|
.m_axi_awprot (replay1_m_axi_awprot),
|
||||||
|
.m_axi_awqos (replay1_m_axi_awqos),
|
||||||
|
.m_axi_awregion (replay1_m_axi_awregion),
|
||||||
|
.m_axi_awuser (replay1_m_axi_awuser),
|
||||||
|
.m_axi_awvalid (replay1_m_axi_awvalid),
|
||||||
|
.m_axi_awready (replay1_m_axi_awready),
|
||||||
|
.m_axi_wdata (replay1_m_axi_wdata),
|
||||||
|
.m_axi_wstrb (replay1_m_axi_wstrb),
|
||||||
|
.m_axi_wlast (replay1_m_axi_wlast),
|
||||||
|
.m_axi_wuser (replay1_m_axi_wuser),
|
||||||
|
.m_axi_wvalid (replay1_m_axi_wvalid),
|
||||||
|
.m_axi_wready (replay1_m_axi_wready),
|
||||||
|
.m_axi_bid (replay1_m_axi_bid),
|
||||||
|
.m_axi_bresp (replay1_m_axi_bresp),
|
||||||
|
.m_axi_buser (replay1_m_axi_buser),
|
||||||
|
.m_axi_bvalid (replay1_m_axi_bvalid),
|
||||||
|
.m_axi_bready (replay1_m_axi_bready),
|
||||||
|
.m_axi_arid (replay1_m_axi_arid),
|
||||||
|
.m_axi_araddr (replay1_m_axi_araddr),
|
||||||
|
.m_axi_arlen (replay1_m_axi_arlen),
|
||||||
|
.m_axi_arsize (replay1_m_axi_arsize),
|
||||||
|
.m_axi_arburst (replay1_m_axi_arburst),
|
||||||
|
.m_axi_arlock (replay1_m_axi_arlock),
|
||||||
|
.m_axi_arcache (replay1_m_axi_arcache),
|
||||||
|
.m_axi_arprot (replay1_m_axi_arprot),
|
||||||
|
.m_axi_arqos (replay1_m_axi_arqos),
|
||||||
|
.m_axi_arregion (replay1_m_axi_arregion),
|
||||||
|
.m_axi_aruser (replay1_m_axi_aruser),
|
||||||
|
.m_axi_arvalid (replay1_m_axi_arvalid),
|
||||||
|
.m_axi_arready (replay1_m_axi_arready),
|
||||||
|
.m_axi_rid (replay1_m_axi_rid),
|
||||||
|
.m_axi_rdata (replay1_m_axi_rdata),
|
||||||
|
.m_axi_rresp (replay1_m_axi_rresp),
|
||||||
|
.m_axi_rlast (replay1_m_axi_rlast),
|
||||||
|
.m_axi_ruser (replay1_m_axi_ruser),
|
||||||
|
.m_axi_rvalid (replay1_m_axi_rvalid),
|
||||||
|
.m_axi_rready (replay1_m_axi_rready),
|
||||||
|
.s_rfnoc_chdr_tdata ({s_replay1_in_1_tdata , s_replay1_in_0_tdata }),
|
||||||
|
.s_rfnoc_chdr_tlast ({s_replay1_in_1_tlast , s_replay1_in_0_tlast }),
|
||||||
|
.s_rfnoc_chdr_tvalid ({s_replay1_in_1_tvalid, s_replay1_in_0_tvalid}),
|
||||||
|
.s_rfnoc_chdr_tready ({s_replay1_in_1_tready, s_replay1_in_0_tready}),
|
||||||
|
.m_rfnoc_chdr_tdata ({m_replay1_out_1_tdata , m_replay1_out_0_tdata }),
|
||||||
|
.m_rfnoc_chdr_tlast ({m_replay1_out_1_tlast , m_replay1_out_0_tlast }),
|
||||||
|
.m_rfnoc_chdr_tvalid ({m_replay1_out_1_tvalid, m_replay1_out_0_tvalid}),
|
||||||
|
.m_rfnoc_chdr_tready ({m_replay1_out_1_tready, m_replay1_out_0_tready}),
|
||||||
|
.s_rfnoc_ctrl_tdata (s_replay1_ctrl_tdata),
|
||||||
|
.s_rfnoc_ctrl_tlast (s_replay1_ctrl_tlast),
|
||||||
|
.s_rfnoc_ctrl_tvalid (s_replay1_ctrl_tvalid),
|
||||||
|
.s_rfnoc_ctrl_tready (s_replay1_ctrl_tready),
|
||||||
|
.m_rfnoc_ctrl_tdata (m_replay1_ctrl_tdata),
|
||||||
|
.m_rfnoc_ctrl_tlast (m_replay1_ctrl_tlast),
|
||||||
|
.m_rfnoc_ctrl_tvalid (m_replay1_ctrl_tvalid),
|
||||||
|
.m_rfnoc_ctrl_tready (m_replay1_ctrl_tready)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Static Router
|
// Static Router
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1361,25 +1548,25 @@ module rfnoc_image_core #(
|
|||||||
assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
|
assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
|
||||||
assign m_replay0_out_1_tready = s_ep5_in0_tready;
|
assign m_replay0_out_1_tready = s_ep5_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_2_tdata = m_ep6_out0_tdata;
|
assign s_replay1_in_0_tdata = m_ep6_out0_tdata;
|
||||||
assign s_replay0_in_2_tlast = m_ep6_out0_tlast;
|
assign s_replay1_in_0_tlast = m_ep6_out0_tlast;
|
||||||
assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid;
|
assign s_replay1_in_0_tvalid = m_ep6_out0_tvalid;
|
||||||
assign m_ep6_out0_tready = s_replay0_in_2_tready;
|
assign m_ep6_out0_tready = s_replay1_in_0_tready;
|
||||||
|
|
||||||
assign s_ep6_in0_tdata = m_replay0_out_2_tdata;
|
assign s_ep6_in0_tdata = m_replay1_out_0_tdata;
|
||||||
assign s_ep6_in0_tlast = m_replay0_out_2_tlast;
|
assign s_ep6_in0_tlast = m_replay1_out_0_tlast;
|
||||||
assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid;
|
assign s_ep6_in0_tvalid = m_replay1_out_0_tvalid;
|
||||||
assign m_replay0_out_2_tready = s_ep6_in0_tready;
|
assign m_replay1_out_0_tready = s_ep6_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_3_tdata = m_ep7_out0_tdata;
|
assign s_replay1_in_1_tdata = m_ep7_out0_tdata;
|
||||||
assign s_replay0_in_3_tlast = m_ep7_out0_tlast;
|
assign s_replay1_in_1_tlast = m_ep7_out0_tlast;
|
||||||
assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid;
|
assign s_replay1_in_1_tvalid = m_ep7_out0_tvalid;
|
||||||
assign m_ep7_out0_tready = s_replay0_in_3_tready;
|
assign m_ep7_out0_tready = s_replay1_in_1_tready;
|
||||||
|
|
||||||
assign s_ep7_in0_tdata = m_replay0_out_3_tdata;
|
assign s_ep7_in0_tdata = m_replay1_out_1_tdata;
|
||||||
assign s_ep7_in0_tlast = m_replay0_out_3_tlast;
|
assign s_ep7_in0_tlast = m_replay1_out_1_tlast;
|
||||||
assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid;
|
assign s_ep7_in0_tvalid = m_replay1_out_1_tvalid;
|
||||||
assign m_replay0_out_3_tready = s_ep7_in0_tready;
|
assign m_replay1_out_1_tready = s_ep7_in0_tready;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1395,6 +1582,7 @@ module rfnoc_image_core #(
|
|||||||
assign radio0_radio_clk = radio_clk;
|
assign radio0_radio_clk = radio_clk;
|
||||||
assign radio1_radio_clk = radio_clk;
|
assign radio1_radio_clk = radio_clk;
|
||||||
assign replay0_mem_clk = dram_clk;
|
assign replay0_mem_clk = dram_clk;
|
||||||
|
assign replay1_mem_clk = dram_clk;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1438,51 +1626,97 @@ module rfnoc_image_core #(
|
|||||||
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
||||||
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
||||||
|
|
||||||
assign replay0_axi_rst = axi_rst;
|
assign replay0_axi_rst = dram0_axi_rst;
|
||||||
assign m_axi_awid = replay0_m_axi_awid;
|
assign dram0_m_axi_awid = replay0_m_axi_awid;
|
||||||
assign m_axi_awaddr = replay0_m_axi_awaddr;
|
assign dram0_m_axi_awaddr = replay0_m_axi_awaddr;
|
||||||
assign m_axi_awlen = replay0_m_axi_awlen;
|
assign dram0_m_axi_awlen = replay0_m_axi_awlen;
|
||||||
assign m_axi_awsize = replay0_m_axi_awsize;
|
assign dram0_m_axi_awsize = replay0_m_axi_awsize;
|
||||||
assign m_axi_awburst = replay0_m_axi_awburst;
|
assign dram0_m_axi_awburst = replay0_m_axi_awburst;
|
||||||
assign m_axi_awlock = replay0_m_axi_awlock;
|
assign dram0_m_axi_awlock = replay0_m_axi_awlock;
|
||||||
assign m_axi_awcache = replay0_m_axi_awcache;
|
assign dram0_m_axi_awcache = replay0_m_axi_awcache;
|
||||||
assign m_axi_awprot = replay0_m_axi_awprot;
|
assign dram0_m_axi_awprot = replay0_m_axi_awprot;
|
||||||
assign m_axi_awqos = replay0_m_axi_awqos;
|
assign dram0_m_axi_awqos = replay0_m_axi_awqos;
|
||||||
assign m_axi_awregion = replay0_m_axi_awregion;
|
assign dram0_m_axi_awregion = replay0_m_axi_awregion;
|
||||||
assign m_axi_awuser = replay0_m_axi_awuser;
|
assign dram0_m_axi_awuser = replay0_m_axi_awuser;
|
||||||
assign m_axi_awvalid = replay0_m_axi_awvalid;
|
assign dram0_m_axi_awvalid = replay0_m_axi_awvalid;
|
||||||
assign replay0_m_axi_awready = m_axi_awready;
|
assign replay0_m_axi_awready = dram0_m_axi_awready;
|
||||||
assign m_axi_wdata = replay0_m_axi_wdata;
|
assign dram0_m_axi_wdata = replay0_m_axi_wdata;
|
||||||
assign m_axi_wstrb = replay0_m_axi_wstrb;
|
assign dram0_m_axi_wstrb = replay0_m_axi_wstrb;
|
||||||
assign m_axi_wlast = replay0_m_axi_wlast;
|
assign dram0_m_axi_wlast = replay0_m_axi_wlast;
|
||||||
assign m_axi_wuser = replay0_m_axi_wuser;
|
assign dram0_m_axi_wuser = replay0_m_axi_wuser;
|
||||||
assign m_axi_wvalid = replay0_m_axi_wvalid;
|
assign dram0_m_axi_wvalid = replay0_m_axi_wvalid;
|
||||||
assign replay0_m_axi_wready = m_axi_wready;
|
assign replay0_m_axi_wready = dram0_m_axi_wready;
|
||||||
assign replay0_m_axi_bid = m_axi_bid;
|
assign replay0_m_axi_bid = dram0_m_axi_bid;
|
||||||
assign replay0_m_axi_bresp = m_axi_bresp;
|
assign replay0_m_axi_bresp = dram0_m_axi_bresp;
|
||||||
assign replay0_m_axi_buser = m_axi_buser;
|
assign replay0_m_axi_buser = dram0_m_axi_buser;
|
||||||
assign replay0_m_axi_bvalid = m_axi_bvalid;
|
assign replay0_m_axi_bvalid = dram0_m_axi_bvalid;
|
||||||
assign m_axi_bready = replay0_m_axi_bready;
|
assign dram0_m_axi_bready = replay0_m_axi_bready;
|
||||||
assign m_axi_arid = replay0_m_axi_arid;
|
assign dram0_m_axi_arid = replay0_m_axi_arid;
|
||||||
assign m_axi_araddr = replay0_m_axi_araddr;
|
assign dram0_m_axi_araddr = replay0_m_axi_araddr;
|
||||||
assign m_axi_arlen = replay0_m_axi_arlen;
|
assign dram0_m_axi_arlen = replay0_m_axi_arlen;
|
||||||
assign m_axi_arsize = replay0_m_axi_arsize;
|
assign dram0_m_axi_arsize = replay0_m_axi_arsize;
|
||||||
assign m_axi_arburst = replay0_m_axi_arburst;
|
assign dram0_m_axi_arburst = replay0_m_axi_arburst;
|
||||||
assign m_axi_arlock = replay0_m_axi_arlock;
|
assign dram0_m_axi_arlock = replay0_m_axi_arlock;
|
||||||
assign m_axi_arcache = replay0_m_axi_arcache;
|
assign dram0_m_axi_arcache = replay0_m_axi_arcache;
|
||||||
assign m_axi_arprot = replay0_m_axi_arprot;
|
assign dram0_m_axi_arprot = replay0_m_axi_arprot;
|
||||||
assign m_axi_arqos = replay0_m_axi_arqos;
|
assign dram0_m_axi_arqos = replay0_m_axi_arqos;
|
||||||
assign m_axi_arregion = replay0_m_axi_arregion;
|
assign dram0_m_axi_arregion = replay0_m_axi_arregion;
|
||||||
assign m_axi_aruser = replay0_m_axi_aruser;
|
assign dram0_m_axi_aruser = replay0_m_axi_aruser;
|
||||||
assign m_axi_arvalid = replay0_m_axi_arvalid;
|
assign dram0_m_axi_arvalid = replay0_m_axi_arvalid;
|
||||||
assign replay0_m_axi_arready = m_axi_arready;
|
assign replay0_m_axi_arready = dram0_m_axi_arready;
|
||||||
assign replay0_m_axi_rid = m_axi_rid;
|
assign replay0_m_axi_rid = dram0_m_axi_rid;
|
||||||
assign replay0_m_axi_rdata = m_axi_rdata;
|
assign replay0_m_axi_rdata = dram0_m_axi_rdata;
|
||||||
assign replay0_m_axi_rresp = m_axi_rresp;
|
assign replay0_m_axi_rresp = dram0_m_axi_rresp;
|
||||||
assign replay0_m_axi_rlast = m_axi_rlast;
|
assign replay0_m_axi_rlast = dram0_m_axi_rlast;
|
||||||
assign replay0_m_axi_ruser = m_axi_ruser;
|
assign replay0_m_axi_ruser = dram0_m_axi_ruser;
|
||||||
assign replay0_m_axi_rvalid = m_axi_rvalid;
|
assign replay0_m_axi_rvalid = dram0_m_axi_rvalid;
|
||||||
assign m_axi_rready = replay0_m_axi_rready;
|
assign dram0_m_axi_rready = replay0_m_axi_rready;
|
||||||
|
|
||||||
|
assign replay1_axi_rst = dram1_axi_rst;
|
||||||
|
assign dram1_m_axi_awid = replay1_m_axi_awid;
|
||||||
|
assign dram1_m_axi_awaddr = replay1_m_axi_awaddr;
|
||||||
|
assign dram1_m_axi_awlen = replay1_m_axi_awlen;
|
||||||
|
assign dram1_m_axi_awsize = replay1_m_axi_awsize;
|
||||||
|
assign dram1_m_axi_awburst = replay1_m_axi_awburst;
|
||||||
|
assign dram1_m_axi_awlock = replay1_m_axi_awlock;
|
||||||
|
assign dram1_m_axi_awcache = replay1_m_axi_awcache;
|
||||||
|
assign dram1_m_axi_awprot = replay1_m_axi_awprot;
|
||||||
|
assign dram1_m_axi_awqos = replay1_m_axi_awqos;
|
||||||
|
assign dram1_m_axi_awregion = replay1_m_axi_awregion;
|
||||||
|
assign dram1_m_axi_awuser = replay1_m_axi_awuser;
|
||||||
|
assign dram1_m_axi_awvalid = replay1_m_axi_awvalid;
|
||||||
|
assign replay1_m_axi_awready = dram1_m_axi_awready;
|
||||||
|
assign dram1_m_axi_wdata = replay1_m_axi_wdata;
|
||||||
|
assign dram1_m_axi_wstrb = replay1_m_axi_wstrb;
|
||||||
|
assign dram1_m_axi_wlast = replay1_m_axi_wlast;
|
||||||
|
assign dram1_m_axi_wuser = replay1_m_axi_wuser;
|
||||||
|
assign dram1_m_axi_wvalid = replay1_m_axi_wvalid;
|
||||||
|
assign replay1_m_axi_wready = dram1_m_axi_wready;
|
||||||
|
assign replay1_m_axi_bid = dram1_m_axi_bid;
|
||||||
|
assign replay1_m_axi_bresp = dram1_m_axi_bresp;
|
||||||
|
assign replay1_m_axi_buser = dram1_m_axi_buser;
|
||||||
|
assign replay1_m_axi_bvalid = dram1_m_axi_bvalid;
|
||||||
|
assign dram1_m_axi_bready = replay1_m_axi_bready;
|
||||||
|
assign dram1_m_axi_arid = replay1_m_axi_arid;
|
||||||
|
assign dram1_m_axi_araddr = replay1_m_axi_araddr;
|
||||||
|
assign dram1_m_axi_arlen = replay1_m_axi_arlen;
|
||||||
|
assign dram1_m_axi_arsize = replay1_m_axi_arsize;
|
||||||
|
assign dram1_m_axi_arburst = replay1_m_axi_arburst;
|
||||||
|
assign dram1_m_axi_arlock = replay1_m_axi_arlock;
|
||||||
|
assign dram1_m_axi_arcache = replay1_m_axi_arcache;
|
||||||
|
assign dram1_m_axi_arprot = replay1_m_axi_arprot;
|
||||||
|
assign dram1_m_axi_arqos = replay1_m_axi_arqos;
|
||||||
|
assign dram1_m_axi_arregion = replay1_m_axi_arregion;
|
||||||
|
assign dram1_m_axi_aruser = replay1_m_axi_aruser;
|
||||||
|
assign dram1_m_axi_arvalid = replay1_m_axi_arvalid;
|
||||||
|
assign replay1_m_axi_arready = dram1_m_axi_arready;
|
||||||
|
assign replay1_m_axi_rid = dram1_m_axi_rid;
|
||||||
|
assign replay1_m_axi_rdata = dram1_m_axi_rdata;
|
||||||
|
assign replay1_m_axi_rresp = dram1_m_axi_rresp;
|
||||||
|
assign replay1_m_axi_rlast = dram1_m_axi_rlast;
|
||||||
|
assign replay1_m_axi_ruser = dram1_m_axi_ruser;
|
||||||
|
assign replay1_m_axi_rvalid = dram1_m_axi_rvalid;
|
||||||
|
assign dram1_m_axi_rready = replay1_m_axi_rready;
|
||||||
|
|
||||||
// Broadcaster/Listener Connections:
|
// Broadcaster/Listener Connections:
|
||||||
assign radio0_radio_time = radio_time;
|
assign radio0_radio_time = radio_time;
|
||||||
|
|||||||
@@ -69,7 +69,13 @@ noc_blocks:
|
|||||||
replay0:
|
replay0:
|
||||||
block_desc: 'replay.yml'
|
block_desc: 'replay.yml'
|
||||||
parameters:
|
parameters:
|
||||||
NUM_PORTS: 4
|
NUM_PORTS: 2
|
||||||
|
MEM_DATA_W: 128
|
||||||
|
MEM_ADDR_W: 32
|
||||||
|
replay1:
|
||||||
|
block_desc: 'replay.yml'
|
||||||
|
parameters:
|
||||||
|
NUM_PORTS: 2
|
||||||
MEM_DATA_W: 128
|
MEM_DATA_W: 128
|
||||||
MEM_ADDR_W: 32
|
MEM_ADDR_W: 32
|
||||||
|
|
||||||
@@ -104,10 +110,10 @@ connections:
|
|||||||
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
||||||
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||||
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
||||||
- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
|
- { srcblk: ep6, srcport: out0, dstblk: replay1, dstport: in_0 }
|
||||||
- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
|
- { srcblk: replay1, srcport: out_0, dstblk: ep6, dstport: in0 }
|
||||||
- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
|
- { srcblk: ep7, srcport: out0, dstblk: replay1, dstport: in_1 }
|
||||||
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
|
- { srcblk: replay1, srcport: out_1, dstblk: ep7, dstport: in0 }
|
||||||
#
|
#
|
||||||
# BSP Connections
|
# BSP Connections
|
||||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||||
@@ -116,7 +122,8 @@ connections:
|
|||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||||
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
||||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
|
||||||
|
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
|
||||||
|
|
||||||
# A list of all clock domain connections in design
|
# A list of all clock domain connections in design
|
||||||
# ------------------------------------------------
|
# ------------------------------------------------
|
||||||
@@ -129,3 +136,4 @@ clk_domains:
|
|||||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||||
|
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
|
||||||
|
|||||||
@@ -11,7 +11,7 @@
|
|||||||
02c00140
|
02c00140
|
||||||
018002c1
|
018002c1
|
||||||
02c10180
|
02c10180
|
||||||
01c002c2
|
01c00300
|
||||||
02c201c0
|
030001c0
|
||||||
020002c3
|
02000301
|
||||||
02c30200
|
03010200
|
||||||
|
|||||||
@@ -36,10 +36,10 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio_clk,
|
input wire radio_clk,
|
||||||
input wire radio_2x_clk,
|
input wire radio_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -83,52 +83,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
|
|||||||
@@ -36,10 +36,10 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio_clk,
|
input wire radio_clk,
|
||||||
input wire radio_2x_clk,
|
input wire radio_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -83,52 +83,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
@@ -1678,51 +1724,51 @@ module rfnoc_image_core #(
|
|||||||
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
|
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
|
||||||
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
|
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
|
||||||
|
|
||||||
assign replay0_axi_rst = axi_rst;
|
assign replay0_axi_rst = dram0_axi_rst;
|
||||||
assign m_axi_awid = replay0_m_axi_awid;
|
assign dram0_m_axi_awid = replay0_m_axi_awid;
|
||||||
assign m_axi_awaddr = replay0_m_axi_awaddr;
|
assign dram0_m_axi_awaddr = replay0_m_axi_awaddr;
|
||||||
assign m_axi_awlen = replay0_m_axi_awlen;
|
assign dram0_m_axi_awlen = replay0_m_axi_awlen;
|
||||||
assign m_axi_awsize = replay0_m_axi_awsize;
|
assign dram0_m_axi_awsize = replay0_m_axi_awsize;
|
||||||
assign m_axi_awburst = replay0_m_axi_awburst;
|
assign dram0_m_axi_awburst = replay0_m_axi_awburst;
|
||||||
assign m_axi_awlock = replay0_m_axi_awlock;
|
assign dram0_m_axi_awlock = replay0_m_axi_awlock;
|
||||||
assign m_axi_awcache = replay0_m_axi_awcache;
|
assign dram0_m_axi_awcache = replay0_m_axi_awcache;
|
||||||
assign m_axi_awprot = replay0_m_axi_awprot;
|
assign dram0_m_axi_awprot = replay0_m_axi_awprot;
|
||||||
assign m_axi_awqos = replay0_m_axi_awqos;
|
assign dram0_m_axi_awqos = replay0_m_axi_awqos;
|
||||||
assign m_axi_awregion = replay0_m_axi_awregion;
|
assign dram0_m_axi_awregion = replay0_m_axi_awregion;
|
||||||
assign m_axi_awuser = replay0_m_axi_awuser;
|
assign dram0_m_axi_awuser = replay0_m_axi_awuser;
|
||||||
assign m_axi_awvalid = replay0_m_axi_awvalid;
|
assign dram0_m_axi_awvalid = replay0_m_axi_awvalid;
|
||||||
assign replay0_m_axi_awready = m_axi_awready;
|
assign replay0_m_axi_awready = dram0_m_axi_awready;
|
||||||
assign m_axi_wdata = replay0_m_axi_wdata;
|
assign dram0_m_axi_wdata = replay0_m_axi_wdata;
|
||||||
assign m_axi_wstrb = replay0_m_axi_wstrb;
|
assign dram0_m_axi_wstrb = replay0_m_axi_wstrb;
|
||||||
assign m_axi_wlast = replay0_m_axi_wlast;
|
assign dram0_m_axi_wlast = replay0_m_axi_wlast;
|
||||||
assign m_axi_wuser = replay0_m_axi_wuser;
|
assign dram0_m_axi_wuser = replay0_m_axi_wuser;
|
||||||
assign m_axi_wvalid = replay0_m_axi_wvalid;
|
assign dram0_m_axi_wvalid = replay0_m_axi_wvalid;
|
||||||
assign replay0_m_axi_wready = m_axi_wready;
|
assign replay0_m_axi_wready = dram0_m_axi_wready;
|
||||||
assign replay0_m_axi_bid = m_axi_bid;
|
assign replay0_m_axi_bid = dram0_m_axi_bid;
|
||||||
assign replay0_m_axi_bresp = m_axi_bresp;
|
assign replay0_m_axi_bresp = dram0_m_axi_bresp;
|
||||||
assign replay0_m_axi_buser = m_axi_buser;
|
assign replay0_m_axi_buser = dram0_m_axi_buser;
|
||||||
assign replay0_m_axi_bvalid = m_axi_bvalid;
|
assign replay0_m_axi_bvalid = dram0_m_axi_bvalid;
|
||||||
assign m_axi_bready = replay0_m_axi_bready;
|
assign dram0_m_axi_bready = replay0_m_axi_bready;
|
||||||
assign m_axi_arid = replay0_m_axi_arid;
|
assign dram0_m_axi_arid = replay0_m_axi_arid;
|
||||||
assign m_axi_araddr = replay0_m_axi_araddr;
|
assign dram0_m_axi_araddr = replay0_m_axi_araddr;
|
||||||
assign m_axi_arlen = replay0_m_axi_arlen;
|
assign dram0_m_axi_arlen = replay0_m_axi_arlen;
|
||||||
assign m_axi_arsize = replay0_m_axi_arsize;
|
assign dram0_m_axi_arsize = replay0_m_axi_arsize;
|
||||||
assign m_axi_arburst = replay0_m_axi_arburst;
|
assign dram0_m_axi_arburst = replay0_m_axi_arburst;
|
||||||
assign m_axi_arlock = replay0_m_axi_arlock;
|
assign dram0_m_axi_arlock = replay0_m_axi_arlock;
|
||||||
assign m_axi_arcache = replay0_m_axi_arcache;
|
assign dram0_m_axi_arcache = replay0_m_axi_arcache;
|
||||||
assign m_axi_arprot = replay0_m_axi_arprot;
|
assign dram0_m_axi_arprot = replay0_m_axi_arprot;
|
||||||
assign m_axi_arqos = replay0_m_axi_arqos;
|
assign dram0_m_axi_arqos = replay0_m_axi_arqos;
|
||||||
assign m_axi_arregion = replay0_m_axi_arregion;
|
assign dram0_m_axi_arregion = replay0_m_axi_arregion;
|
||||||
assign m_axi_aruser = replay0_m_axi_aruser;
|
assign dram0_m_axi_aruser = replay0_m_axi_aruser;
|
||||||
assign m_axi_arvalid = replay0_m_axi_arvalid;
|
assign dram0_m_axi_arvalid = replay0_m_axi_arvalid;
|
||||||
assign replay0_m_axi_arready = m_axi_arready;
|
assign replay0_m_axi_arready = dram0_m_axi_arready;
|
||||||
assign replay0_m_axi_rid = m_axi_rid;
|
assign replay0_m_axi_rid = dram0_m_axi_rid;
|
||||||
assign replay0_m_axi_rdata = m_axi_rdata;
|
assign replay0_m_axi_rdata = dram0_m_axi_rdata;
|
||||||
assign replay0_m_axi_rresp = m_axi_rresp;
|
assign replay0_m_axi_rresp = dram0_m_axi_rresp;
|
||||||
assign replay0_m_axi_rlast = m_axi_rlast;
|
assign replay0_m_axi_rlast = dram0_m_axi_rlast;
|
||||||
assign replay0_m_axi_ruser = m_axi_ruser;
|
assign replay0_m_axi_ruser = dram0_m_axi_ruser;
|
||||||
assign replay0_m_axi_rvalid = m_axi_rvalid;
|
assign replay0_m_axi_rvalid = dram0_m_axi_rvalid;
|
||||||
assign m_axi_rready = replay0_m_axi_rready;
|
assign dram0_m_axi_rready = replay0_m_axi_rready;
|
||||||
|
|
||||||
// Broadcaster/Listener Connections:
|
// Broadcaster/Listener Connections:
|
||||||
assign radio0_radio_time = radio_time;
|
assign radio0_radio_time = radio_time;
|
||||||
|
|||||||
@@ -149,7 +149,7 @@ connections:
|
|||||||
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
||||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||||
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
||||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
|
||||||
|
|
||||||
# A list of all clock domain connections in design
|
# A list of all clock domain connections in design
|
||||||
# ------------------------------------------------
|
# ------------------------------------------------
|
||||||
|
|||||||
@@ -36,10 +36,10 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio_clk,
|
input wire radio_clk,
|
||||||
input wire radio_2x_clk,
|
input wire radio_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -83,52 +83,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
|
|||||||
@@ -36,12 +36,12 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio0_clk,
|
input wire radio0_clk,
|
||||||
input wire radio1_clk,
|
input wire radio1_clk,
|
||||||
input wire radio0_2x_clk,
|
input wire radio0_2x_clk,
|
||||||
input wire radio1_2x_clk,
|
input wire radio1_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -87,52 +87,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
@@ -596,10 +642,14 @@ module rfnoc_image_core #(
|
|||||||
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
||||||
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
||||||
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
||||||
|
wire [31:0] m_replay1_ctrl_tdata, s_replay1_ctrl_tdata;
|
||||||
|
wire m_replay1_ctrl_tlast, s_replay1_ctrl_tlast;
|
||||||
|
wire m_replay1_ctrl_tvalid, s_replay1_ctrl_tvalid;
|
||||||
|
wire m_replay1_ctrl_tready, s_replay1_ctrl_tready;
|
||||||
|
|
||||||
axis_ctrl_crossbar_nxn #(
|
axis_ctrl_crossbar_nxn #(
|
||||||
.WIDTH (32),
|
.WIDTH (32),
|
||||||
.NPORTS (5),
|
.NPORTS (6),
|
||||||
.TOPOLOGY ("TORUS"),
|
.TOPOLOGY ("TORUS"),
|
||||||
.INGRESS_BUFF_SIZE(5),
|
.INGRESS_BUFF_SIZE(5),
|
||||||
.ROUTER_BUFF_SIZE (5),
|
.ROUTER_BUFF_SIZE (5),
|
||||||
@@ -608,14 +658,14 @@ module rfnoc_image_core #(
|
|||||||
) ctrl_xb_i (
|
) ctrl_xb_i (
|
||||||
.clk (rfnoc_ctrl_clk),
|
.clk (rfnoc_ctrl_clk),
|
||||||
.reset (rfnoc_ctrl_rst),
|
.reset (rfnoc_ctrl_rst),
|
||||||
.s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
.s_axis_tdata ({m_replay1_ctrl_tdata , m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
||||||
.s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
.s_axis_tvalid ({m_replay1_ctrl_tvalid, m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
||||||
.s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
.s_axis_tlast ({m_replay1_ctrl_tlast , m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
||||||
.s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
.s_axis_tready ({m_replay1_ctrl_tready, m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
||||||
.m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
.m_axis_tdata ({s_replay1_ctrl_tdata , s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
||||||
.m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
.m_axis_tvalid ({s_replay1_ctrl_tvalid, s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
||||||
.m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
.m_axis_tlast ({s_replay1_ctrl_tlast , s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
||||||
.m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
.m_axis_tready ({s_replay1_ctrl_tready, s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
||||||
.deadlock_detected()
|
.deadlock_detected()
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -624,14 +674,14 @@ module rfnoc_image_core #(
|
|||||||
// RFNoC Core Kernel
|
// RFNoC Core Kernel
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
|
wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
|
||||||
|
|
||||||
rfnoc_core_kernel #(
|
rfnoc_core_kernel #(
|
||||||
.PROTOVER (PROTOVER),
|
.PROTOVER (PROTOVER),
|
||||||
.DEVICE_TYPE (16'hA400),
|
.DEVICE_TYPE (16'hA400),
|
||||||
.DEVICE_FAMILY ("ULTRASCALE"),
|
.DEVICE_FAMILY ("ULTRASCALE"),
|
||||||
.SAFE_START_CLKS (0),
|
.SAFE_START_CLKS (0),
|
||||||
.NUM_BLOCKS (3),
|
.NUM_BLOCKS (4),
|
||||||
.NUM_STREAM_ENDPOINTS(4),
|
.NUM_STREAM_ENDPOINTS(4),
|
||||||
.NUM_ENDPOINTS_CTRL (1),
|
.NUM_ENDPOINTS_CTRL (1),
|
||||||
.NUM_TRANSPORTS (6),
|
.NUM_TRANSPORTS (6),
|
||||||
@@ -841,14 +891,14 @@ module rfnoc_image_core #(
|
|||||||
//-----------------------------------
|
//-----------------------------------
|
||||||
|
|
||||||
wire replay0_mem_clk;
|
wire replay0_mem_clk;
|
||||||
wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] s_replay0_in_0_tdata ;
|
||||||
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
|
wire s_replay0_in_0_tlast ;
|
||||||
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
|
wire s_replay0_in_0_tvalid;
|
||||||
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
|
wire s_replay0_in_0_tready;
|
||||||
wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] m_replay0_out_0_tdata ;
|
||||||
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
|
wire m_replay0_out_0_tlast ;
|
||||||
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
|
wire m_replay0_out_0_tvalid;
|
||||||
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
|
wire m_replay0_out_0_tready;
|
||||||
|
|
||||||
// axi_ram
|
// axi_ram
|
||||||
wire [ 0:0] replay0_axi_rst;
|
wire [ 0:0] replay0_axi_rst;
|
||||||
@@ -900,7 +950,7 @@ module rfnoc_image_core #(
|
|||||||
rfnoc_block_replay #(
|
rfnoc_block_replay #(
|
||||||
.THIS_PORTID (4),
|
.THIS_PORTID (4),
|
||||||
.CHDR_W (BLOCK_CHDR_W),
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
.NUM_PORTS (2),
|
.NUM_PORTS (1),
|
||||||
.MEM_DATA_W (512),
|
.MEM_DATA_W (512),
|
||||||
.MEM_ADDR_W (32),
|
.MEM_ADDR_W (32),
|
||||||
.MTU (BLOCK_MTU)
|
.MTU (BLOCK_MTU)
|
||||||
@@ -955,14 +1005,14 @@ module rfnoc_image_core #(
|
|||||||
.m_axi_ruser (replay0_m_axi_ruser),
|
.m_axi_ruser (replay0_m_axi_ruser),
|
||||||
.m_axi_rvalid (replay0_m_axi_rvalid),
|
.m_axi_rvalid (replay0_m_axi_rvalid),
|
||||||
.m_axi_rready (replay0_m_axi_rready),
|
.m_axi_rready (replay0_m_axi_rready),
|
||||||
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
|
.s_rfnoc_chdr_tdata ({s_replay0_in_0_tdata }),
|
||||||
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
|
.s_rfnoc_chdr_tlast ({s_replay0_in_0_tlast }),
|
||||||
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
|
.s_rfnoc_chdr_tvalid ({s_replay0_in_0_tvalid}),
|
||||||
.s_rfnoc_chdr_tready ({s_replay0_in_1_tready, s_replay0_in_0_tready}),
|
.s_rfnoc_chdr_tready ({s_replay0_in_0_tready}),
|
||||||
.m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
|
.m_rfnoc_chdr_tdata ({m_replay0_out_0_tdata }),
|
||||||
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
|
.m_rfnoc_chdr_tlast ({m_replay0_out_0_tlast }),
|
||||||
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
|
.m_rfnoc_chdr_tvalid ({m_replay0_out_0_tvalid}),
|
||||||
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
|
.m_rfnoc_chdr_tready ({m_replay0_out_0_tready}),
|
||||||
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
||||||
@@ -973,6 +1023,143 @@ module rfnoc_image_core #(
|
|||||||
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//-----------------------------------
|
||||||
|
// replay1
|
||||||
|
//-----------------------------------
|
||||||
|
|
||||||
|
wire replay1_mem_clk;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] s_replay1_in_0_tdata ;
|
||||||
|
wire s_replay1_in_0_tlast ;
|
||||||
|
wire s_replay1_in_0_tvalid;
|
||||||
|
wire s_replay1_in_0_tready;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] m_replay1_out_0_tdata ;
|
||||||
|
wire m_replay1_out_0_tlast ;
|
||||||
|
wire m_replay1_out_0_tvalid;
|
||||||
|
wire m_replay1_out_0_tready;
|
||||||
|
|
||||||
|
// axi_ram
|
||||||
|
wire [ 0:0] replay1_axi_rst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awid;
|
||||||
|
wire [ 383:0] replay1_m_axi_awaddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_awlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_awsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_awburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_awcache;
|
||||||
|
wire [ 23:0] replay1_m_axi_awprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_awqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_awregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_awuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_awvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_awready;
|
||||||
|
wire [4191:0] replay1_m_axi_wdata;
|
||||||
|
wire [ 511:0] replay1_m_axi_wstrb;
|
||||||
|
wire [ 7:0] replay1_m_axi_wlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_wuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_wvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_wready;
|
||||||
|
wire [ 7:0] replay1_m_axi_bid;
|
||||||
|
wire [ 15:0] replay1_m_axi_bresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_buser;
|
||||||
|
wire [ 7:0] replay1_m_axi_bvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_bready;
|
||||||
|
wire [ 7:0] replay1_m_axi_arid;
|
||||||
|
wire [ 383:0] replay1_m_axi_araddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_arlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_arsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_arburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_arlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_arcache;
|
||||||
|
wire [ 31:0] replay1_m_axi_arprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_arqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_arregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_aruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_arvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_arready;
|
||||||
|
wire [ 7:0] replay1_m_axi_rid;
|
||||||
|
wire [4191:0] replay1_m_axi_rdata;
|
||||||
|
wire [ 15:0] replay1_m_axi_rresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_rlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_ruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_rvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_rready;
|
||||||
|
|
||||||
|
rfnoc_block_replay #(
|
||||||
|
.THIS_PORTID (5),
|
||||||
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
|
.NUM_PORTS (1),
|
||||||
|
.MEM_DATA_W (512),
|
||||||
|
.MEM_ADDR_W (32),
|
||||||
|
.MTU (BLOCK_MTU)
|
||||||
|
) b_replay1_3 (
|
||||||
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.mem_clk (replay1_mem_clk),
|
||||||
|
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
|
||||||
|
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
|
||||||
|
.axi_rst (replay1_axi_rst),
|
||||||
|
.m_axi_awid (replay1_m_axi_awid),
|
||||||
|
.m_axi_awaddr (replay1_m_axi_awaddr),
|
||||||
|
.m_axi_awlen (replay1_m_axi_awlen),
|
||||||
|
.m_axi_awsize (replay1_m_axi_awsize),
|
||||||
|
.m_axi_awburst (replay1_m_axi_awburst),
|
||||||
|
.m_axi_awlock (replay1_m_axi_awlock),
|
||||||
|
.m_axi_awcache (replay1_m_axi_awcache),
|
||||||
|
.m_axi_awprot (replay1_m_axi_awprot),
|
||||||
|
.m_axi_awqos (replay1_m_axi_awqos),
|
||||||
|
.m_axi_awregion (replay1_m_axi_awregion),
|
||||||
|
.m_axi_awuser (replay1_m_axi_awuser),
|
||||||
|
.m_axi_awvalid (replay1_m_axi_awvalid),
|
||||||
|
.m_axi_awready (replay1_m_axi_awready),
|
||||||
|
.m_axi_wdata (replay1_m_axi_wdata),
|
||||||
|
.m_axi_wstrb (replay1_m_axi_wstrb),
|
||||||
|
.m_axi_wlast (replay1_m_axi_wlast),
|
||||||
|
.m_axi_wuser (replay1_m_axi_wuser),
|
||||||
|
.m_axi_wvalid (replay1_m_axi_wvalid),
|
||||||
|
.m_axi_wready (replay1_m_axi_wready),
|
||||||
|
.m_axi_bid (replay1_m_axi_bid),
|
||||||
|
.m_axi_bresp (replay1_m_axi_bresp),
|
||||||
|
.m_axi_buser (replay1_m_axi_buser),
|
||||||
|
.m_axi_bvalid (replay1_m_axi_bvalid),
|
||||||
|
.m_axi_bready (replay1_m_axi_bready),
|
||||||
|
.m_axi_arid (replay1_m_axi_arid),
|
||||||
|
.m_axi_araddr (replay1_m_axi_araddr),
|
||||||
|
.m_axi_arlen (replay1_m_axi_arlen),
|
||||||
|
.m_axi_arsize (replay1_m_axi_arsize),
|
||||||
|
.m_axi_arburst (replay1_m_axi_arburst),
|
||||||
|
.m_axi_arlock (replay1_m_axi_arlock),
|
||||||
|
.m_axi_arcache (replay1_m_axi_arcache),
|
||||||
|
.m_axi_arprot (replay1_m_axi_arprot),
|
||||||
|
.m_axi_arqos (replay1_m_axi_arqos),
|
||||||
|
.m_axi_arregion (replay1_m_axi_arregion),
|
||||||
|
.m_axi_aruser (replay1_m_axi_aruser),
|
||||||
|
.m_axi_arvalid (replay1_m_axi_arvalid),
|
||||||
|
.m_axi_arready (replay1_m_axi_arready),
|
||||||
|
.m_axi_rid (replay1_m_axi_rid),
|
||||||
|
.m_axi_rdata (replay1_m_axi_rdata),
|
||||||
|
.m_axi_rresp (replay1_m_axi_rresp),
|
||||||
|
.m_axi_rlast (replay1_m_axi_rlast),
|
||||||
|
.m_axi_ruser (replay1_m_axi_ruser),
|
||||||
|
.m_axi_rvalid (replay1_m_axi_rvalid),
|
||||||
|
.m_axi_rready (replay1_m_axi_rready),
|
||||||
|
.s_rfnoc_chdr_tdata ({s_replay1_in_0_tdata }),
|
||||||
|
.s_rfnoc_chdr_tlast ({s_replay1_in_0_tlast }),
|
||||||
|
.s_rfnoc_chdr_tvalid ({s_replay1_in_0_tvalid}),
|
||||||
|
.s_rfnoc_chdr_tready ({s_replay1_in_0_tready}),
|
||||||
|
.m_rfnoc_chdr_tdata ({m_replay1_out_0_tdata }),
|
||||||
|
.m_rfnoc_chdr_tlast ({m_replay1_out_0_tlast }),
|
||||||
|
.m_rfnoc_chdr_tvalid ({m_replay1_out_0_tvalid}),
|
||||||
|
.m_rfnoc_chdr_tready ({m_replay1_out_0_tready}),
|
||||||
|
.s_rfnoc_ctrl_tdata (s_replay1_ctrl_tdata),
|
||||||
|
.s_rfnoc_ctrl_tlast (s_replay1_ctrl_tlast),
|
||||||
|
.s_rfnoc_ctrl_tvalid (s_replay1_ctrl_tvalid),
|
||||||
|
.s_rfnoc_ctrl_tready (s_replay1_ctrl_tready),
|
||||||
|
.m_rfnoc_ctrl_tdata (m_replay1_ctrl_tdata),
|
||||||
|
.m_rfnoc_ctrl_tlast (m_replay1_ctrl_tlast),
|
||||||
|
.m_rfnoc_ctrl_tvalid (m_replay1_ctrl_tvalid),
|
||||||
|
.m_rfnoc_ctrl_tready (m_replay1_ctrl_tready)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Static Router
|
// Static Router
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1007,15 +1194,15 @@ module rfnoc_image_core #(
|
|||||||
assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
|
assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
|
||||||
assign m_replay0_out_0_tready = s_ep2_in0_tready;
|
assign m_replay0_out_0_tready = s_ep2_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_1_tdata = m_ep3_out0_tdata;
|
assign s_replay1_in_0_tdata = m_ep3_out0_tdata;
|
||||||
assign s_replay0_in_1_tlast = m_ep3_out0_tlast;
|
assign s_replay1_in_0_tlast = m_ep3_out0_tlast;
|
||||||
assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid;
|
assign s_replay1_in_0_tvalid = m_ep3_out0_tvalid;
|
||||||
assign m_ep3_out0_tready = s_replay0_in_1_tready;
|
assign m_ep3_out0_tready = s_replay1_in_0_tready;
|
||||||
|
|
||||||
assign s_ep3_in0_tdata = m_replay0_out_1_tdata;
|
assign s_ep3_in0_tdata = m_replay1_out_0_tdata;
|
||||||
assign s_ep3_in0_tlast = m_replay0_out_1_tlast;
|
assign s_ep3_in0_tlast = m_replay1_out_0_tlast;
|
||||||
assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid;
|
assign s_ep3_in0_tvalid = m_replay1_out_0_tvalid;
|
||||||
assign m_replay0_out_1_tready = s_ep3_in0_tready;
|
assign m_replay1_out_0_tready = s_ep3_in0_tready;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1031,6 +1218,7 @@ module rfnoc_image_core #(
|
|||||||
assign radio0_radio_clk = radio0_clk;
|
assign radio0_radio_clk = radio0_clk;
|
||||||
assign radio1_radio_clk = radio1_clk;
|
assign radio1_radio_clk = radio1_clk;
|
||||||
assign replay0_mem_clk = dram_clk;
|
assign replay0_mem_clk = dram_clk;
|
||||||
|
assign replay1_mem_clk = dram_clk;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -1074,51 +1262,97 @@ module rfnoc_image_core #(
|
|||||||
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
||||||
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
||||||
|
|
||||||
assign replay0_axi_rst = axi_rst;
|
assign replay0_axi_rst = dram0_axi_rst;
|
||||||
assign m_axi_awid = replay0_m_axi_awid;
|
assign dram0_m_axi_awid = replay0_m_axi_awid;
|
||||||
assign m_axi_awaddr = replay0_m_axi_awaddr;
|
assign dram0_m_axi_awaddr = replay0_m_axi_awaddr;
|
||||||
assign m_axi_awlen = replay0_m_axi_awlen;
|
assign dram0_m_axi_awlen = replay0_m_axi_awlen;
|
||||||
assign m_axi_awsize = replay0_m_axi_awsize;
|
assign dram0_m_axi_awsize = replay0_m_axi_awsize;
|
||||||
assign m_axi_awburst = replay0_m_axi_awburst;
|
assign dram0_m_axi_awburst = replay0_m_axi_awburst;
|
||||||
assign m_axi_awlock = replay0_m_axi_awlock;
|
assign dram0_m_axi_awlock = replay0_m_axi_awlock;
|
||||||
assign m_axi_awcache = replay0_m_axi_awcache;
|
assign dram0_m_axi_awcache = replay0_m_axi_awcache;
|
||||||
assign m_axi_awprot = replay0_m_axi_awprot;
|
assign dram0_m_axi_awprot = replay0_m_axi_awprot;
|
||||||
assign m_axi_awqos = replay0_m_axi_awqos;
|
assign dram0_m_axi_awqos = replay0_m_axi_awqos;
|
||||||
assign m_axi_awregion = replay0_m_axi_awregion;
|
assign dram0_m_axi_awregion = replay0_m_axi_awregion;
|
||||||
assign m_axi_awuser = replay0_m_axi_awuser;
|
assign dram0_m_axi_awuser = replay0_m_axi_awuser;
|
||||||
assign m_axi_awvalid = replay0_m_axi_awvalid;
|
assign dram0_m_axi_awvalid = replay0_m_axi_awvalid;
|
||||||
assign replay0_m_axi_awready = m_axi_awready;
|
assign replay0_m_axi_awready = dram0_m_axi_awready;
|
||||||
assign m_axi_wdata = replay0_m_axi_wdata;
|
assign dram0_m_axi_wdata = replay0_m_axi_wdata;
|
||||||
assign m_axi_wstrb = replay0_m_axi_wstrb;
|
assign dram0_m_axi_wstrb = replay0_m_axi_wstrb;
|
||||||
assign m_axi_wlast = replay0_m_axi_wlast;
|
assign dram0_m_axi_wlast = replay0_m_axi_wlast;
|
||||||
assign m_axi_wuser = replay0_m_axi_wuser;
|
assign dram0_m_axi_wuser = replay0_m_axi_wuser;
|
||||||
assign m_axi_wvalid = replay0_m_axi_wvalid;
|
assign dram0_m_axi_wvalid = replay0_m_axi_wvalid;
|
||||||
assign replay0_m_axi_wready = m_axi_wready;
|
assign replay0_m_axi_wready = dram0_m_axi_wready;
|
||||||
assign replay0_m_axi_bid = m_axi_bid;
|
assign replay0_m_axi_bid = dram0_m_axi_bid;
|
||||||
assign replay0_m_axi_bresp = m_axi_bresp;
|
assign replay0_m_axi_bresp = dram0_m_axi_bresp;
|
||||||
assign replay0_m_axi_buser = m_axi_buser;
|
assign replay0_m_axi_buser = dram0_m_axi_buser;
|
||||||
assign replay0_m_axi_bvalid = m_axi_bvalid;
|
assign replay0_m_axi_bvalid = dram0_m_axi_bvalid;
|
||||||
assign m_axi_bready = replay0_m_axi_bready;
|
assign dram0_m_axi_bready = replay0_m_axi_bready;
|
||||||
assign m_axi_arid = replay0_m_axi_arid;
|
assign dram0_m_axi_arid = replay0_m_axi_arid;
|
||||||
assign m_axi_araddr = replay0_m_axi_araddr;
|
assign dram0_m_axi_araddr = replay0_m_axi_araddr;
|
||||||
assign m_axi_arlen = replay0_m_axi_arlen;
|
assign dram0_m_axi_arlen = replay0_m_axi_arlen;
|
||||||
assign m_axi_arsize = replay0_m_axi_arsize;
|
assign dram0_m_axi_arsize = replay0_m_axi_arsize;
|
||||||
assign m_axi_arburst = replay0_m_axi_arburst;
|
assign dram0_m_axi_arburst = replay0_m_axi_arburst;
|
||||||
assign m_axi_arlock = replay0_m_axi_arlock;
|
assign dram0_m_axi_arlock = replay0_m_axi_arlock;
|
||||||
assign m_axi_arcache = replay0_m_axi_arcache;
|
assign dram0_m_axi_arcache = replay0_m_axi_arcache;
|
||||||
assign m_axi_arprot = replay0_m_axi_arprot;
|
assign dram0_m_axi_arprot = replay0_m_axi_arprot;
|
||||||
assign m_axi_arqos = replay0_m_axi_arqos;
|
assign dram0_m_axi_arqos = replay0_m_axi_arqos;
|
||||||
assign m_axi_arregion = replay0_m_axi_arregion;
|
assign dram0_m_axi_arregion = replay0_m_axi_arregion;
|
||||||
assign m_axi_aruser = replay0_m_axi_aruser;
|
assign dram0_m_axi_aruser = replay0_m_axi_aruser;
|
||||||
assign m_axi_arvalid = replay0_m_axi_arvalid;
|
assign dram0_m_axi_arvalid = replay0_m_axi_arvalid;
|
||||||
assign replay0_m_axi_arready = m_axi_arready;
|
assign replay0_m_axi_arready = dram0_m_axi_arready;
|
||||||
assign replay0_m_axi_rid = m_axi_rid;
|
assign replay0_m_axi_rid = dram0_m_axi_rid;
|
||||||
assign replay0_m_axi_rdata = m_axi_rdata;
|
assign replay0_m_axi_rdata = dram0_m_axi_rdata;
|
||||||
assign replay0_m_axi_rresp = m_axi_rresp;
|
assign replay0_m_axi_rresp = dram0_m_axi_rresp;
|
||||||
assign replay0_m_axi_rlast = m_axi_rlast;
|
assign replay0_m_axi_rlast = dram0_m_axi_rlast;
|
||||||
assign replay0_m_axi_ruser = m_axi_ruser;
|
assign replay0_m_axi_ruser = dram0_m_axi_ruser;
|
||||||
assign replay0_m_axi_rvalid = m_axi_rvalid;
|
assign replay0_m_axi_rvalid = dram0_m_axi_rvalid;
|
||||||
assign m_axi_rready = replay0_m_axi_rready;
|
assign dram0_m_axi_rready = replay0_m_axi_rready;
|
||||||
|
|
||||||
|
assign replay1_axi_rst = dram1_axi_rst;
|
||||||
|
assign dram1_m_axi_awid = replay1_m_axi_awid;
|
||||||
|
assign dram1_m_axi_awaddr = replay1_m_axi_awaddr;
|
||||||
|
assign dram1_m_axi_awlen = replay1_m_axi_awlen;
|
||||||
|
assign dram1_m_axi_awsize = replay1_m_axi_awsize;
|
||||||
|
assign dram1_m_axi_awburst = replay1_m_axi_awburst;
|
||||||
|
assign dram1_m_axi_awlock = replay1_m_axi_awlock;
|
||||||
|
assign dram1_m_axi_awcache = replay1_m_axi_awcache;
|
||||||
|
assign dram1_m_axi_awprot = replay1_m_axi_awprot;
|
||||||
|
assign dram1_m_axi_awqos = replay1_m_axi_awqos;
|
||||||
|
assign dram1_m_axi_awregion = replay1_m_axi_awregion;
|
||||||
|
assign dram1_m_axi_awuser = replay1_m_axi_awuser;
|
||||||
|
assign dram1_m_axi_awvalid = replay1_m_axi_awvalid;
|
||||||
|
assign replay1_m_axi_awready = dram1_m_axi_awready;
|
||||||
|
assign dram1_m_axi_wdata = replay1_m_axi_wdata;
|
||||||
|
assign dram1_m_axi_wstrb = replay1_m_axi_wstrb;
|
||||||
|
assign dram1_m_axi_wlast = replay1_m_axi_wlast;
|
||||||
|
assign dram1_m_axi_wuser = replay1_m_axi_wuser;
|
||||||
|
assign dram1_m_axi_wvalid = replay1_m_axi_wvalid;
|
||||||
|
assign replay1_m_axi_wready = dram1_m_axi_wready;
|
||||||
|
assign replay1_m_axi_bid = dram1_m_axi_bid;
|
||||||
|
assign replay1_m_axi_bresp = dram1_m_axi_bresp;
|
||||||
|
assign replay1_m_axi_buser = dram1_m_axi_buser;
|
||||||
|
assign replay1_m_axi_bvalid = dram1_m_axi_bvalid;
|
||||||
|
assign dram1_m_axi_bready = replay1_m_axi_bready;
|
||||||
|
assign dram1_m_axi_arid = replay1_m_axi_arid;
|
||||||
|
assign dram1_m_axi_araddr = replay1_m_axi_araddr;
|
||||||
|
assign dram1_m_axi_arlen = replay1_m_axi_arlen;
|
||||||
|
assign dram1_m_axi_arsize = replay1_m_axi_arsize;
|
||||||
|
assign dram1_m_axi_arburst = replay1_m_axi_arburst;
|
||||||
|
assign dram1_m_axi_arlock = replay1_m_axi_arlock;
|
||||||
|
assign dram1_m_axi_arcache = replay1_m_axi_arcache;
|
||||||
|
assign dram1_m_axi_arprot = replay1_m_axi_arprot;
|
||||||
|
assign dram1_m_axi_arqos = replay1_m_axi_arqos;
|
||||||
|
assign dram1_m_axi_arregion = replay1_m_axi_arregion;
|
||||||
|
assign dram1_m_axi_aruser = replay1_m_axi_aruser;
|
||||||
|
assign dram1_m_axi_arvalid = replay1_m_axi_arvalid;
|
||||||
|
assign replay1_m_axi_arready = dram1_m_axi_arready;
|
||||||
|
assign replay1_m_axi_rid = dram1_m_axi_rid;
|
||||||
|
assign replay1_m_axi_rdata = dram1_m_axi_rdata;
|
||||||
|
assign replay1_m_axi_rresp = dram1_m_axi_rresp;
|
||||||
|
assign replay1_m_axi_rlast = dram1_m_axi_rlast;
|
||||||
|
assign replay1_m_axi_ruser = dram1_m_axi_ruser;
|
||||||
|
assign replay1_m_axi_rvalid = dram1_m_axi_rvalid;
|
||||||
|
assign dram1_m_axi_rready = replay1_m_axi_rready;
|
||||||
|
|
||||||
// Broadcaster/Listener Connections:
|
// Broadcaster/Listener Connections:
|
||||||
assign radio0_radio_time = radio_time0;
|
assign radio0_radio_time = radio_time0;
|
||||||
|
|||||||
@@ -71,7 +71,13 @@ noc_blocks:
|
|||||||
replay0:
|
replay0:
|
||||||
block_desc: 'replay.yml'
|
block_desc: 'replay.yml'
|
||||||
parameters:
|
parameters:
|
||||||
NUM_PORTS: 2
|
NUM_PORTS: 1
|
||||||
|
MEM_DATA_W: 512
|
||||||
|
MEM_ADDR_W: 32
|
||||||
|
replay1:
|
||||||
|
block_desc: 'replay.yml'
|
||||||
|
parameters:
|
||||||
|
NUM_PORTS: 1
|
||||||
MEM_DATA_W: 512
|
MEM_DATA_W: 512
|
||||||
MEM_ADDR_W: 32
|
MEM_ADDR_W: 32
|
||||||
|
|
||||||
@@ -97,8 +103,8 @@ connections:
|
|||||||
# Replay Connections
|
# Replay Connections
|
||||||
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
|
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||||
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
|
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
|
||||||
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
|
- { srcblk: ep3, srcport: out0, dstblk: replay1, dstport: in_0 }
|
||||||
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
|
- { srcblk: replay1, srcport: out_0, dstblk: ep3, dstport: in0 }
|
||||||
#
|
#
|
||||||
# BSP Connections
|
# BSP Connections
|
||||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||||
@@ -107,7 +113,8 @@ connections:
|
|||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
|
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
|
||||||
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
|
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
|
||||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
|
||||||
|
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
|
||||||
|
|
||||||
# A list of all clock domain connections in design
|
# A list of all clock domain connections in design
|
||||||
# ------------------------------------------------
|
# ------------------------------------------------
|
||||||
@@ -120,3 +127,4 @@ clk_domains:
|
|||||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||||
|
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
|
||||||
|
|||||||
@@ -5,5 +5,5 @@
|
|||||||
01800080
|
01800080
|
||||||
00c001c0
|
00c001c0
|
||||||
01c000c0
|
01c000c0
|
||||||
010001c1
|
01000200
|
||||||
01c10100
|
02000100
|
||||||
|
|||||||
@@ -36,12 +36,12 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio0_clk,
|
input wire radio0_clk,
|
||||||
input wire radio1_clk,
|
input wire radio1_clk,
|
||||||
input wire radio0_2x_clk,
|
input wire radio0_2x_clk,
|
||||||
input wire radio1_2x_clk,
|
input wire radio1_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -87,52 +87,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
|
|||||||
@@ -36,12 +36,12 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio0_clk,
|
input wire radio0_clk,
|
||||||
input wire radio1_clk,
|
input wire radio1_clk,
|
||||||
input wire radio0_2x_clk,
|
input wire radio0_2x_clk,
|
||||||
input wire radio1_2x_clk,
|
input wire radio1_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -87,52 +87,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
@@ -1580,10 +1626,14 @@ module rfnoc_image_core #(
|
|||||||
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast;
|
||||||
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
|
||||||
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
|
||||||
|
wire [31:0] m_replay1_ctrl_tdata, s_replay1_ctrl_tdata;
|
||||||
|
wire m_replay1_ctrl_tlast, s_replay1_ctrl_tlast;
|
||||||
|
wire m_replay1_ctrl_tvalid, s_replay1_ctrl_tvalid;
|
||||||
|
wire m_replay1_ctrl_tready, s_replay1_ctrl_tready;
|
||||||
|
|
||||||
axis_ctrl_crossbar_nxn #(
|
axis_ctrl_crossbar_nxn #(
|
||||||
.WIDTH (32),
|
.WIDTH (32),
|
||||||
.NPORTS (5),
|
.NPORTS (6),
|
||||||
.TOPOLOGY ("TORUS"),
|
.TOPOLOGY ("TORUS"),
|
||||||
.INGRESS_BUFF_SIZE(5),
|
.INGRESS_BUFF_SIZE(5),
|
||||||
.ROUTER_BUFF_SIZE (5),
|
.ROUTER_BUFF_SIZE (5),
|
||||||
@@ -1592,14 +1642,14 @@ module rfnoc_image_core #(
|
|||||||
) ctrl_xb_i (
|
) ctrl_xb_i (
|
||||||
.clk (rfnoc_ctrl_clk),
|
.clk (rfnoc_ctrl_clk),
|
||||||
.reset (rfnoc_ctrl_rst),
|
.reset (rfnoc_ctrl_rst),
|
||||||
.s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
.s_axis_tdata ({m_replay1_ctrl_tdata , m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
||||||
.s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
.s_axis_tvalid ({m_replay1_ctrl_tvalid, m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
||||||
.s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
.s_axis_tlast ({m_replay1_ctrl_tlast , m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
||||||
.s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
.s_axis_tready ({m_replay1_ctrl_tready, m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
||||||
.m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
.m_axis_tdata ({s_replay1_ctrl_tdata , s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
||||||
.m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
.m_axis_tvalid ({s_replay1_ctrl_tvalid, s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
||||||
.m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
.m_axis_tlast ({s_replay1_ctrl_tlast , s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
||||||
.m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
.m_axis_tready ({s_replay1_ctrl_tready, s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
||||||
.deadlock_detected()
|
.deadlock_detected()
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -1608,14 +1658,14 @@ module rfnoc_image_core #(
|
|||||||
// RFNoC Core Kernel
|
// RFNoC Core Kernel
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
|
wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
|
||||||
|
|
||||||
rfnoc_core_kernel #(
|
rfnoc_core_kernel #(
|
||||||
.PROTOVER (PROTOVER),
|
.PROTOVER (PROTOVER),
|
||||||
.DEVICE_TYPE (16'hA400),
|
.DEVICE_TYPE (16'hA400),
|
||||||
.DEVICE_FAMILY ("ULTRASCALE"),
|
.DEVICE_FAMILY ("ULTRASCALE"),
|
||||||
.SAFE_START_CLKS (0),
|
.SAFE_START_CLKS (0),
|
||||||
.NUM_BLOCKS (3),
|
.NUM_BLOCKS (4),
|
||||||
.NUM_STREAM_ENDPOINTS(16),
|
.NUM_STREAM_ENDPOINTS(16),
|
||||||
.NUM_ENDPOINTS_CTRL (1),
|
.NUM_ENDPOINTS_CTRL (1),
|
||||||
.NUM_TRANSPORTS (6),
|
.NUM_TRANSPORTS (6),
|
||||||
@@ -1825,14 +1875,14 @@ module rfnoc_image_core #(
|
|||||||
//-----------------------------------
|
//-----------------------------------
|
||||||
|
|
||||||
wire replay0_mem_clk;
|
wire replay0_mem_clk;
|
||||||
wire [BLOCK_CHDR_W-1:0] s_replay0_in_7_tdata , s_replay0_in_6_tdata , s_replay0_in_5_tdata , s_replay0_in_4_tdata , s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
|
||||||
wire s_replay0_in_7_tlast , s_replay0_in_6_tlast , s_replay0_in_5_tlast , s_replay0_in_4_tlast , s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
|
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
|
||||||
wire s_replay0_in_7_tvalid, s_replay0_in_6_tvalid, s_replay0_in_5_tvalid, s_replay0_in_4_tvalid, s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
|
wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
|
||||||
wire s_replay0_in_7_tready, s_replay0_in_6_tready, s_replay0_in_5_tready, s_replay0_in_4_tready, s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
|
wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
|
||||||
wire [BLOCK_CHDR_W-1:0] m_replay0_out_7_tdata , m_replay0_out_6_tdata , m_replay0_out_5_tdata , m_replay0_out_4_tdata , m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
|
wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
|
||||||
wire m_replay0_out_7_tlast , m_replay0_out_6_tlast , m_replay0_out_5_tlast , m_replay0_out_4_tlast , m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
|
wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
|
||||||
wire m_replay0_out_7_tvalid, m_replay0_out_6_tvalid, m_replay0_out_5_tvalid, m_replay0_out_4_tvalid, m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
|
wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
|
||||||
wire m_replay0_out_7_tready, m_replay0_out_6_tready, m_replay0_out_5_tready, m_replay0_out_4_tready, m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
|
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
|
||||||
|
|
||||||
// axi_ram
|
// axi_ram
|
||||||
wire [ 0:0] replay0_axi_rst;
|
wire [ 0:0] replay0_axi_rst;
|
||||||
@@ -1884,7 +1934,7 @@ module rfnoc_image_core #(
|
|||||||
rfnoc_block_replay #(
|
rfnoc_block_replay #(
|
||||||
.THIS_PORTID (4),
|
.THIS_PORTID (4),
|
||||||
.CHDR_W (BLOCK_CHDR_W),
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
.NUM_PORTS (8),
|
.NUM_PORTS (4),
|
||||||
.MEM_DATA_W (128),
|
.MEM_DATA_W (128),
|
||||||
.MEM_ADDR_W (32),
|
.MEM_ADDR_W (32),
|
||||||
.MTU (BLOCK_MTU)
|
.MTU (BLOCK_MTU)
|
||||||
@@ -1939,14 +1989,14 @@ module rfnoc_image_core #(
|
|||||||
.m_axi_ruser (replay0_m_axi_ruser),
|
.m_axi_ruser (replay0_m_axi_ruser),
|
||||||
.m_axi_rvalid (replay0_m_axi_rvalid),
|
.m_axi_rvalid (replay0_m_axi_rvalid),
|
||||||
.m_axi_rready (replay0_m_axi_rready),
|
.m_axi_rready (replay0_m_axi_rready),
|
||||||
.s_rfnoc_chdr_tdata ({s_replay0_in_7_tdata , s_replay0_in_6_tdata , s_replay0_in_5_tdata , s_replay0_in_4_tdata , s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
|
.s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
|
||||||
.s_rfnoc_chdr_tlast ({s_replay0_in_7_tlast , s_replay0_in_6_tlast , s_replay0_in_5_tlast , s_replay0_in_4_tlast , s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
|
.s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
|
||||||
.s_rfnoc_chdr_tvalid ({s_replay0_in_7_tvalid, s_replay0_in_6_tvalid, s_replay0_in_5_tvalid, s_replay0_in_4_tvalid, s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
|
.s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
|
||||||
.s_rfnoc_chdr_tready ({s_replay0_in_7_tready, s_replay0_in_6_tready, s_replay0_in_5_tready, s_replay0_in_4_tready, s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
|
.s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
|
||||||
.m_rfnoc_chdr_tdata ({m_replay0_out_7_tdata , m_replay0_out_6_tdata , m_replay0_out_5_tdata , m_replay0_out_4_tdata , m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
|
.m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
|
||||||
.m_rfnoc_chdr_tlast ({m_replay0_out_7_tlast , m_replay0_out_6_tlast , m_replay0_out_5_tlast , m_replay0_out_4_tlast , m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
|
.m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
|
||||||
.m_rfnoc_chdr_tvalid ({m_replay0_out_7_tvalid, m_replay0_out_6_tvalid, m_replay0_out_5_tvalid, m_replay0_out_4_tvalid, m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
|
.m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
|
||||||
.m_rfnoc_chdr_tready ({m_replay0_out_7_tready, m_replay0_out_6_tready, m_replay0_out_5_tready, m_replay0_out_4_tready, m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
|
.m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
|
||||||
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
|
||||||
@@ -1957,6 +2007,143 @@ module rfnoc_image_core #(
|
|||||||
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//-----------------------------------
|
||||||
|
// replay1
|
||||||
|
//-----------------------------------
|
||||||
|
|
||||||
|
wire replay1_mem_clk;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] s_replay1_in_3_tdata , s_replay1_in_2_tdata , s_replay1_in_1_tdata , s_replay1_in_0_tdata ;
|
||||||
|
wire s_replay1_in_3_tlast , s_replay1_in_2_tlast , s_replay1_in_1_tlast , s_replay1_in_0_tlast ;
|
||||||
|
wire s_replay1_in_3_tvalid, s_replay1_in_2_tvalid, s_replay1_in_1_tvalid, s_replay1_in_0_tvalid;
|
||||||
|
wire s_replay1_in_3_tready, s_replay1_in_2_tready, s_replay1_in_1_tready, s_replay1_in_0_tready;
|
||||||
|
wire [BLOCK_CHDR_W-1:0] m_replay1_out_3_tdata , m_replay1_out_2_tdata , m_replay1_out_1_tdata , m_replay1_out_0_tdata ;
|
||||||
|
wire m_replay1_out_3_tlast , m_replay1_out_2_tlast , m_replay1_out_1_tlast , m_replay1_out_0_tlast ;
|
||||||
|
wire m_replay1_out_3_tvalid, m_replay1_out_2_tvalid, m_replay1_out_1_tvalid, m_replay1_out_0_tvalid;
|
||||||
|
wire m_replay1_out_3_tready, m_replay1_out_2_tready, m_replay1_out_1_tready, m_replay1_out_0_tready;
|
||||||
|
|
||||||
|
// axi_ram
|
||||||
|
wire [ 0:0] replay1_axi_rst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awid;
|
||||||
|
wire [ 383:0] replay1_m_axi_awaddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_awlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_awsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_awburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_awlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_awcache;
|
||||||
|
wire [ 23:0] replay1_m_axi_awprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_awqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_awregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_awuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_awvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_awready;
|
||||||
|
wire [4191:0] replay1_m_axi_wdata;
|
||||||
|
wire [ 511:0] replay1_m_axi_wstrb;
|
||||||
|
wire [ 7:0] replay1_m_axi_wlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_wuser;
|
||||||
|
wire [ 7:0] replay1_m_axi_wvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_wready;
|
||||||
|
wire [ 7:0] replay1_m_axi_bid;
|
||||||
|
wire [ 15:0] replay1_m_axi_bresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_buser;
|
||||||
|
wire [ 7:0] replay1_m_axi_bvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_bready;
|
||||||
|
wire [ 7:0] replay1_m_axi_arid;
|
||||||
|
wire [ 383:0] replay1_m_axi_araddr;
|
||||||
|
wire [ 63:0] replay1_m_axi_arlen;
|
||||||
|
wire [ 23:0] replay1_m_axi_arsize;
|
||||||
|
wire [ 15:0] replay1_m_axi_arburst;
|
||||||
|
wire [ 7:0] replay1_m_axi_arlock;
|
||||||
|
wire [ 31:0] replay1_m_axi_arcache;
|
||||||
|
wire [ 31:0] replay1_m_axi_arprot;
|
||||||
|
wire [ 31:0] replay1_m_axi_arqos;
|
||||||
|
wire [ 31:0] replay1_m_axi_arregion;
|
||||||
|
wire [ 7:0] replay1_m_axi_aruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_arvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_arready;
|
||||||
|
wire [ 7:0] replay1_m_axi_rid;
|
||||||
|
wire [4191:0] replay1_m_axi_rdata;
|
||||||
|
wire [ 15:0] replay1_m_axi_rresp;
|
||||||
|
wire [ 7:0] replay1_m_axi_rlast;
|
||||||
|
wire [ 7:0] replay1_m_axi_ruser;
|
||||||
|
wire [ 7:0] replay1_m_axi_rvalid;
|
||||||
|
wire [ 7:0] replay1_m_axi_rready;
|
||||||
|
|
||||||
|
rfnoc_block_replay #(
|
||||||
|
.THIS_PORTID (5),
|
||||||
|
.CHDR_W (BLOCK_CHDR_W),
|
||||||
|
.NUM_PORTS (4),
|
||||||
|
.MEM_DATA_W (128),
|
||||||
|
.MEM_ADDR_W (32),
|
||||||
|
.MTU (BLOCK_MTU)
|
||||||
|
) b_replay1_3 (
|
||||||
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.mem_clk (replay1_mem_clk),
|
||||||
|
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
|
||||||
|
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
|
||||||
|
.axi_rst (replay1_axi_rst),
|
||||||
|
.m_axi_awid (replay1_m_axi_awid),
|
||||||
|
.m_axi_awaddr (replay1_m_axi_awaddr),
|
||||||
|
.m_axi_awlen (replay1_m_axi_awlen),
|
||||||
|
.m_axi_awsize (replay1_m_axi_awsize),
|
||||||
|
.m_axi_awburst (replay1_m_axi_awburst),
|
||||||
|
.m_axi_awlock (replay1_m_axi_awlock),
|
||||||
|
.m_axi_awcache (replay1_m_axi_awcache),
|
||||||
|
.m_axi_awprot (replay1_m_axi_awprot),
|
||||||
|
.m_axi_awqos (replay1_m_axi_awqos),
|
||||||
|
.m_axi_awregion (replay1_m_axi_awregion),
|
||||||
|
.m_axi_awuser (replay1_m_axi_awuser),
|
||||||
|
.m_axi_awvalid (replay1_m_axi_awvalid),
|
||||||
|
.m_axi_awready (replay1_m_axi_awready),
|
||||||
|
.m_axi_wdata (replay1_m_axi_wdata),
|
||||||
|
.m_axi_wstrb (replay1_m_axi_wstrb),
|
||||||
|
.m_axi_wlast (replay1_m_axi_wlast),
|
||||||
|
.m_axi_wuser (replay1_m_axi_wuser),
|
||||||
|
.m_axi_wvalid (replay1_m_axi_wvalid),
|
||||||
|
.m_axi_wready (replay1_m_axi_wready),
|
||||||
|
.m_axi_bid (replay1_m_axi_bid),
|
||||||
|
.m_axi_bresp (replay1_m_axi_bresp),
|
||||||
|
.m_axi_buser (replay1_m_axi_buser),
|
||||||
|
.m_axi_bvalid (replay1_m_axi_bvalid),
|
||||||
|
.m_axi_bready (replay1_m_axi_bready),
|
||||||
|
.m_axi_arid (replay1_m_axi_arid),
|
||||||
|
.m_axi_araddr (replay1_m_axi_araddr),
|
||||||
|
.m_axi_arlen (replay1_m_axi_arlen),
|
||||||
|
.m_axi_arsize (replay1_m_axi_arsize),
|
||||||
|
.m_axi_arburst (replay1_m_axi_arburst),
|
||||||
|
.m_axi_arlock (replay1_m_axi_arlock),
|
||||||
|
.m_axi_arcache (replay1_m_axi_arcache),
|
||||||
|
.m_axi_arprot (replay1_m_axi_arprot),
|
||||||
|
.m_axi_arqos (replay1_m_axi_arqos),
|
||||||
|
.m_axi_arregion (replay1_m_axi_arregion),
|
||||||
|
.m_axi_aruser (replay1_m_axi_aruser),
|
||||||
|
.m_axi_arvalid (replay1_m_axi_arvalid),
|
||||||
|
.m_axi_arready (replay1_m_axi_arready),
|
||||||
|
.m_axi_rid (replay1_m_axi_rid),
|
||||||
|
.m_axi_rdata (replay1_m_axi_rdata),
|
||||||
|
.m_axi_rresp (replay1_m_axi_rresp),
|
||||||
|
.m_axi_rlast (replay1_m_axi_rlast),
|
||||||
|
.m_axi_ruser (replay1_m_axi_ruser),
|
||||||
|
.m_axi_rvalid (replay1_m_axi_rvalid),
|
||||||
|
.m_axi_rready (replay1_m_axi_rready),
|
||||||
|
.s_rfnoc_chdr_tdata ({s_replay1_in_3_tdata , s_replay1_in_2_tdata , s_replay1_in_1_tdata , s_replay1_in_0_tdata }),
|
||||||
|
.s_rfnoc_chdr_tlast ({s_replay1_in_3_tlast , s_replay1_in_2_tlast , s_replay1_in_1_tlast , s_replay1_in_0_tlast }),
|
||||||
|
.s_rfnoc_chdr_tvalid ({s_replay1_in_3_tvalid, s_replay1_in_2_tvalid, s_replay1_in_1_tvalid, s_replay1_in_0_tvalid}),
|
||||||
|
.s_rfnoc_chdr_tready ({s_replay1_in_3_tready, s_replay1_in_2_tready, s_replay1_in_1_tready, s_replay1_in_0_tready}),
|
||||||
|
.m_rfnoc_chdr_tdata ({m_replay1_out_3_tdata , m_replay1_out_2_tdata , m_replay1_out_1_tdata , m_replay1_out_0_tdata }),
|
||||||
|
.m_rfnoc_chdr_tlast ({m_replay1_out_3_tlast , m_replay1_out_2_tlast , m_replay1_out_1_tlast , m_replay1_out_0_tlast }),
|
||||||
|
.m_rfnoc_chdr_tvalid ({m_replay1_out_3_tvalid, m_replay1_out_2_tvalid, m_replay1_out_1_tvalid, m_replay1_out_0_tvalid}),
|
||||||
|
.m_rfnoc_chdr_tready ({m_replay1_out_3_tready, m_replay1_out_2_tready, m_replay1_out_1_tready, m_replay1_out_0_tready}),
|
||||||
|
.s_rfnoc_ctrl_tdata (s_replay1_ctrl_tdata),
|
||||||
|
.s_rfnoc_ctrl_tlast (s_replay1_ctrl_tlast),
|
||||||
|
.s_rfnoc_ctrl_tvalid (s_replay1_ctrl_tvalid),
|
||||||
|
.s_rfnoc_ctrl_tready (s_replay1_ctrl_tready),
|
||||||
|
.m_rfnoc_ctrl_tdata (m_replay1_ctrl_tdata),
|
||||||
|
.m_rfnoc_ctrl_tlast (m_replay1_ctrl_tlast),
|
||||||
|
.m_rfnoc_ctrl_tvalid (m_replay1_ctrl_tvalid),
|
||||||
|
.m_rfnoc_ctrl_tready (m_replay1_ctrl_tready)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Static Router
|
// Static Router
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -2081,45 +2268,45 @@ module rfnoc_image_core #(
|
|||||||
assign s_ep11_in0_tvalid = m_replay0_out_3_tvalid;
|
assign s_ep11_in0_tvalid = m_replay0_out_3_tvalid;
|
||||||
assign m_replay0_out_3_tready = s_ep11_in0_tready;
|
assign m_replay0_out_3_tready = s_ep11_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_4_tdata = m_ep12_out0_tdata;
|
assign s_replay1_in_0_tdata = m_ep12_out0_tdata;
|
||||||
assign s_replay0_in_4_tlast = m_ep12_out0_tlast;
|
assign s_replay1_in_0_tlast = m_ep12_out0_tlast;
|
||||||
assign s_replay0_in_4_tvalid = m_ep12_out0_tvalid;
|
assign s_replay1_in_0_tvalid = m_ep12_out0_tvalid;
|
||||||
assign m_ep12_out0_tready = s_replay0_in_4_tready;
|
assign m_ep12_out0_tready = s_replay1_in_0_tready;
|
||||||
|
|
||||||
assign s_ep12_in0_tdata = m_replay0_out_4_tdata;
|
assign s_ep12_in0_tdata = m_replay1_out_0_tdata;
|
||||||
assign s_ep12_in0_tlast = m_replay0_out_4_tlast;
|
assign s_ep12_in0_tlast = m_replay1_out_0_tlast;
|
||||||
assign s_ep12_in0_tvalid = m_replay0_out_4_tvalid;
|
assign s_ep12_in0_tvalid = m_replay1_out_0_tvalid;
|
||||||
assign m_replay0_out_4_tready = s_ep12_in0_tready;
|
assign m_replay1_out_0_tready = s_ep12_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_5_tdata = m_ep13_out0_tdata;
|
assign s_replay1_in_1_tdata = m_ep13_out0_tdata;
|
||||||
assign s_replay0_in_5_tlast = m_ep13_out0_tlast;
|
assign s_replay1_in_1_tlast = m_ep13_out0_tlast;
|
||||||
assign s_replay0_in_5_tvalid = m_ep13_out0_tvalid;
|
assign s_replay1_in_1_tvalid = m_ep13_out0_tvalid;
|
||||||
assign m_ep13_out0_tready = s_replay0_in_5_tready;
|
assign m_ep13_out0_tready = s_replay1_in_1_tready;
|
||||||
|
|
||||||
assign s_ep13_in0_tdata = m_replay0_out_5_tdata;
|
assign s_ep13_in0_tdata = m_replay1_out_1_tdata;
|
||||||
assign s_ep13_in0_tlast = m_replay0_out_5_tlast;
|
assign s_ep13_in0_tlast = m_replay1_out_1_tlast;
|
||||||
assign s_ep13_in0_tvalid = m_replay0_out_5_tvalid;
|
assign s_ep13_in0_tvalid = m_replay1_out_1_tvalid;
|
||||||
assign m_replay0_out_5_tready = s_ep13_in0_tready;
|
assign m_replay1_out_1_tready = s_ep13_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_6_tdata = m_ep14_out0_tdata;
|
assign s_replay1_in_2_tdata = m_ep14_out0_tdata;
|
||||||
assign s_replay0_in_6_tlast = m_ep14_out0_tlast;
|
assign s_replay1_in_2_tlast = m_ep14_out0_tlast;
|
||||||
assign s_replay0_in_6_tvalid = m_ep14_out0_tvalid;
|
assign s_replay1_in_2_tvalid = m_ep14_out0_tvalid;
|
||||||
assign m_ep14_out0_tready = s_replay0_in_6_tready;
|
assign m_ep14_out0_tready = s_replay1_in_2_tready;
|
||||||
|
|
||||||
assign s_ep14_in0_tdata = m_replay0_out_6_tdata;
|
assign s_ep14_in0_tdata = m_replay1_out_2_tdata;
|
||||||
assign s_ep14_in0_tlast = m_replay0_out_6_tlast;
|
assign s_ep14_in0_tlast = m_replay1_out_2_tlast;
|
||||||
assign s_ep14_in0_tvalid = m_replay0_out_6_tvalid;
|
assign s_ep14_in0_tvalid = m_replay1_out_2_tvalid;
|
||||||
assign m_replay0_out_6_tready = s_ep14_in0_tready;
|
assign m_replay1_out_2_tready = s_ep14_in0_tready;
|
||||||
|
|
||||||
assign s_replay0_in_7_tdata = m_ep15_out0_tdata;
|
assign s_replay1_in_3_tdata = m_ep15_out0_tdata;
|
||||||
assign s_replay0_in_7_tlast = m_ep15_out0_tlast;
|
assign s_replay1_in_3_tlast = m_ep15_out0_tlast;
|
||||||
assign s_replay0_in_7_tvalid = m_ep15_out0_tvalid;
|
assign s_replay1_in_3_tvalid = m_ep15_out0_tvalid;
|
||||||
assign m_ep15_out0_tready = s_replay0_in_7_tready;
|
assign m_ep15_out0_tready = s_replay1_in_3_tready;
|
||||||
|
|
||||||
assign s_ep15_in0_tdata = m_replay0_out_7_tdata;
|
assign s_ep15_in0_tdata = m_replay1_out_3_tdata;
|
||||||
assign s_ep15_in0_tlast = m_replay0_out_7_tlast;
|
assign s_ep15_in0_tlast = m_replay1_out_3_tlast;
|
||||||
assign s_ep15_in0_tvalid = m_replay0_out_7_tvalid;
|
assign s_ep15_in0_tvalid = m_replay1_out_3_tvalid;
|
||||||
assign m_replay0_out_7_tready = s_ep15_in0_tready;
|
assign m_replay1_out_3_tready = s_ep15_in0_tready;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -2135,6 +2322,7 @@ module rfnoc_image_core #(
|
|||||||
assign radio0_radio_clk = radio0_clk;
|
assign radio0_radio_clk = radio0_clk;
|
||||||
assign radio1_radio_clk = radio1_clk;
|
assign radio1_radio_clk = radio1_clk;
|
||||||
assign replay0_mem_clk = dram_clk;
|
assign replay0_mem_clk = dram_clk;
|
||||||
|
assign replay1_mem_clk = dram_clk;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -2178,51 +2366,97 @@ module rfnoc_image_core #(
|
|||||||
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
|
||||||
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
assign radio_tx_running_radio1 = radio1_radio_tx_running;
|
||||||
|
|
||||||
assign replay0_axi_rst = axi_rst;
|
assign replay0_axi_rst = dram0_axi_rst;
|
||||||
assign m_axi_awid = replay0_m_axi_awid;
|
assign dram0_m_axi_awid = replay0_m_axi_awid;
|
||||||
assign m_axi_awaddr = replay0_m_axi_awaddr;
|
assign dram0_m_axi_awaddr = replay0_m_axi_awaddr;
|
||||||
assign m_axi_awlen = replay0_m_axi_awlen;
|
assign dram0_m_axi_awlen = replay0_m_axi_awlen;
|
||||||
assign m_axi_awsize = replay0_m_axi_awsize;
|
assign dram0_m_axi_awsize = replay0_m_axi_awsize;
|
||||||
assign m_axi_awburst = replay0_m_axi_awburst;
|
assign dram0_m_axi_awburst = replay0_m_axi_awburst;
|
||||||
assign m_axi_awlock = replay0_m_axi_awlock;
|
assign dram0_m_axi_awlock = replay0_m_axi_awlock;
|
||||||
assign m_axi_awcache = replay0_m_axi_awcache;
|
assign dram0_m_axi_awcache = replay0_m_axi_awcache;
|
||||||
assign m_axi_awprot = replay0_m_axi_awprot;
|
assign dram0_m_axi_awprot = replay0_m_axi_awprot;
|
||||||
assign m_axi_awqos = replay0_m_axi_awqos;
|
assign dram0_m_axi_awqos = replay0_m_axi_awqos;
|
||||||
assign m_axi_awregion = replay0_m_axi_awregion;
|
assign dram0_m_axi_awregion = replay0_m_axi_awregion;
|
||||||
assign m_axi_awuser = replay0_m_axi_awuser;
|
assign dram0_m_axi_awuser = replay0_m_axi_awuser;
|
||||||
assign m_axi_awvalid = replay0_m_axi_awvalid;
|
assign dram0_m_axi_awvalid = replay0_m_axi_awvalid;
|
||||||
assign replay0_m_axi_awready = m_axi_awready;
|
assign replay0_m_axi_awready = dram0_m_axi_awready;
|
||||||
assign m_axi_wdata = replay0_m_axi_wdata;
|
assign dram0_m_axi_wdata = replay0_m_axi_wdata;
|
||||||
assign m_axi_wstrb = replay0_m_axi_wstrb;
|
assign dram0_m_axi_wstrb = replay0_m_axi_wstrb;
|
||||||
assign m_axi_wlast = replay0_m_axi_wlast;
|
assign dram0_m_axi_wlast = replay0_m_axi_wlast;
|
||||||
assign m_axi_wuser = replay0_m_axi_wuser;
|
assign dram0_m_axi_wuser = replay0_m_axi_wuser;
|
||||||
assign m_axi_wvalid = replay0_m_axi_wvalid;
|
assign dram0_m_axi_wvalid = replay0_m_axi_wvalid;
|
||||||
assign replay0_m_axi_wready = m_axi_wready;
|
assign replay0_m_axi_wready = dram0_m_axi_wready;
|
||||||
assign replay0_m_axi_bid = m_axi_bid;
|
assign replay0_m_axi_bid = dram0_m_axi_bid;
|
||||||
assign replay0_m_axi_bresp = m_axi_bresp;
|
assign replay0_m_axi_bresp = dram0_m_axi_bresp;
|
||||||
assign replay0_m_axi_buser = m_axi_buser;
|
assign replay0_m_axi_buser = dram0_m_axi_buser;
|
||||||
assign replay0_m_axi_bvalid = m_axi_bvalid;
|
assign replay0_m_axi_bvalid = dram0_m_axi_bvalid;
|
||||||
assign m_axi_bready = replay0_m_axi_bready;
|
assign dram0_m_axi_bready = replay0_m_axi_bready;
|
||||||
assign m_axi_arid = replay0_m_axi_arid;
|
assign dram0_m_axi_arid = replay0_m_axi_arid;
|
||||||
assign m_axi_araddr = replay0_m_axi_araddr;
|
assign dram0_m_axi_araddr = replay0_m_axi_araddr;
|
||||||
assign m_axi_arlen = replay0_m_axi_arlen;
|
assign dram0_m_axi_arlen = replay0_m_axi_arlen;
|
||||||
assign m_axi_arsize = replay0_m_axi_arsize;
|
assign dram0_m_axi_arsize = replay0_m_axi_arsize;
|
||||||
assign m_axi_arburst = replay0_m_axi_arburst;
|
assign dram0_m_axi_arburst = replay0_m_axi_arburst;
|
||||||
assign m_axi_arlock = replay0_m_axi_arlock;
|
assign dram0_m_axi_arlock = replay0_m_axi_arlock;
|
||||||
assign m_axi_arcache = replay0_m_axi_arcache;
|
assign dram0_m_axi_arcache = replay0_m_axi_arcache;
|
||||||
assign m_axi_arprot = replay0_m_axi_arprot;
|
assign dram0_m_axi_arprot = replay0_m_axi_arprot;
|
||||||
assign m_axi_arqos = replay0_m_axi_arqos;
|
assign dram0_m_axi_arqos = replay0_m_axi_arqos;
|
||||||
assign m_axi_arregion = replay0_m_axi_arregion;
|
assign dram0_m_axi_arregion = replay0_m_axi_arregion;
|
||||||
assign m_axi_aruser = replay0_m_axi_aruser;
|
assign dram0_m_axi_aruser = replay0_m_axi_aruser;
|
||||||
assign m_axi_arvalid = replay0_m_axi_arvalid;
|
assign dram0_m_axi_arvalid = replay0_m_axi_arvalid;
|
||||||
assign replay0_m_axi_arready = m_axi_arready;
|
assign replay0_m_axi_arready = dram0_m_axi_arready;
|
||||||
assign replay0_m_axi_rid = m_axi_rid;
|
assign replay0_m_axi_rid = dram0_m_axi_rid;
|
||||||
assign replay0_m_axi_rdata = m_axi_rdata;
|
assign replay0_m_axi_rdata = dram0_m_axi_rdata;
|
||||||
assign replay0_m_axi_rresp = m_axi_rresp;
|
assign replay0_m_axi_rresp = dram0_m_axi_rresp;
|
||||||
assign replay0_m_axi_rlast = m_axi_rlast;
|
assign replay0_m_axi_rlast = dram0_m_axi_rlast;
|
||||||
assign replay0_m_axi_ruser = m_axi_ruser;
|
assign replay0_m_axi_ruser = dram0_m_axi_ruser;
|
||||||
assign replay0_m_axi_rvalid = m_axi_rvalid;
|
assign replay0_m_axi_rvalid = dram0_m_axi_rvalid;
|
||||||
assign m_axi_rready = replay0_m_axi_rready;
|
assign dram0_m_axi_rready = replay0_m_axi_rready;
|
||||||
|
|
||||||
|
assign replay1_axi_rst = dram1_axi_rst;
|
||||||
|
assign dram1_m_axi_awid = replay1_m_axi_awid;
|
||||||
|
assign dram1_m_axi_awaddr = replay1_m_axi_awaddr;
|
||||||
|
assign dram1_m_axi_awlen = replay1_m_axi_awlen;
|
||||||
|
assign dram1_m_axi_awsize = replay1_m_axi_awsize;
|
||||||
|
assign dram1_m_axi_awburst = replay1_m_axi_awburst;
|
||||||
|
assign dram1_m_axi_awlock = replay1_m_axi_awlock;
|
||||||
|
assign dram1_m_axi_awcache = replay1_m_axi_awcache;
|
||||||
|
assign dram1_m_axi_awprot = replay1_m_axi_awprot;
|
||||||
|
assign dram1_m_axi_awqos = replay1_m_axi_awqos;
|
||||||
|
assign dram1_m_axi_awregion = replay1_m_axi_awregion;
|
||||||
|
assign dram1_m_axi_awuser = replay1_m_axi_awuser;
|
||||||
|
assign dram1_m_axi_awvalid = replay1_m_axi_awvalid;
|
||||||
|
assign replay1_m_axi_awready = dram1_m_axi_awready;
|
||||||
|
assign dram1_m_axi_wdata = replay1_m_axi_wdata;
|
||||||
|
assign dram1_m_axi_wstrb = replay1_m_axi_wstrb;
|
||||||
|
assign dram1_m_axi_wlast = replay1_m_axi_wlast;
|
||||||
|
assign dram1_m_axi_wuser = replay1_m_axi_wuser;
|
||||||
|
assign dram1_m_axi_wvalid = replay1_m_axi_wvalid;
|
||||||
|
assign replay1_m_axi_wready = dram1_m_axi_wready;
|
||||||
|
assign replay1_m_axi_bid = dram1_m_axi_bid;
|
||||||
|
assign replay1_m_axi_bresp = dram1_m_axi_bresp;
|
||||||
|
assign replay1_m_axi_buser = dram1_m_axi_buser;
|
||||||
|
assign replay1_m_axi_bvalid = dram1_m_axi_bvalid;
|
||||||
|
assign dram1_m_axi_bready = replay1_m_axi_bready;
|
||||||
|
assign dram1_m_axi_arid = replay1_m_axi_arid;
|
||||||
|
assign dram1_m_axi_araddr = replay1_m_axi_araddr;
|
||||||
|
assign dram1_m_axi_arlen = replay1_m_axi_arlen;
|
||||||
|
assign dram1_m_axi_arsize = replay1_m_axi_arsize;
|
||||||
|
assign dram1_m_axi_arburst = replay1_m_axi_arburst;
|
||||||
|
assign dram1_m_axi_arlock = replay1_m_axi_arlock;
|
||||||
|
assign dram1_m_axi_arcache = replay1_m_axi_arcache;
|
||||||
|
assign dram1_m_axi_arprot = replay1_m_axi_arprot;
|
||||||
|
assign dram1_m_axi_arqos = replay1_m_axi_arqos;
|
||||||
|
assign dram1_m_axi_arregion = replay1_m_axi_arregion;
|
||||||
|
assign dram1_m_axi_aruser = replay1_m_axi_aruser;
|
||||||
|
assign dram1_m_axi_arvalid = replay1_m_axi_arvalid;
|
||||||
|
assign replay1_m_axi_arready = dram1_m_axi_arready;
|
||||||
|
assign replay1_m_axi_rid = dram1_m_axi_rid;
|
||||||
|
assign replay1_m_axi_rdata = dram1_m_axi_rdata;
|
||||||
|
assign replay1_m_axi_rresp = dram1_m_axi_rresp;
|
||||||
|
assign replay1_m_axi_rlast = dram1_m_axi_rlast;
|
||||||
|
assign replay1_m_axi_ruser = dram1_m_axi_ruser;
|
||||||
|
assign replay1_m_axi_rvalid = dram1_m_axi_rvalid;
|
||||||
|
assign dram1_m_axi_rready = replay1_m_axi_rready;
|
||||||
|
|
||||||
// Broadcaster/Listener Connections:
|
// Broadcaster/Listener Connections:
|
||||||
assign radio0_radio_time = radio_time0;
|
assign radio0_radio_time = radio_time0;
|
||||||
|
|||||||
@@ -131,7 +131,13 @@ noc_blocks:
|
|||||||
replay0:
|
replay0:
|
||||||
block_desc: 'replay.yml'
|
block_desc: 'replay.yml'
|
||||||
parameters:
|
parameters:
|
||||||
NUM_PORTS: 8
|
NUM_PORTS: 4
|
||||||
|
MEM_DATA_W: 128
|
||||||
|
MEM_ADDR_W: 32
|
||||||
|
replay1:
|
||||||
|
block_desc: 'replay.yml'
|
||||||
|
parameters:
|
||||||
|
NUM_PORTS: 4
|
||||||
MEM_DATA_W: 128
|
MEM_DATA_W: 128
|
||||||
MEM_ADDR_W: 32
|
MEM_ADDR_W: 32
|
||||||
|
|
||||||
@@ -186,14 +192,14 @@ connections:
|
|||||||
- { srcblk: replay0, srcport: out_2, dstblk: ep10, dstport: in0 }
|
- { srcblk: replay0, srcport: out_2, dstblk: ep10, dstport: in0 }
|
||||||
- { srcblk: ep11, srcport: out0, dstblk: replay0, dstport: in_3 }
|
- { srcblk: ep11, srcport: out0, dstblk: replay0, dstport: in_3 }
|
||||||
- { srcblk: replay0, srcport: out_3, dstblk: ep11, dstport: in0 }
|
- { srcblk: replay0, srcport: out_3, dstblk: ep11, dstport: in0 }
|
||||||
- { srcblk: ep12, srcport: out0, dstblk: replay0, dstport: in_4 }
|
- { srcblk: ep12, srcport: out0, dstblk: replay1, dstport: in_0 }
|
||||||
- { srcblk: replay0, srcport: out_4, dstblk: ep12, dstport: in0 }
|
- { srcblk: replay1, srcport: out_0, dstblk: ep12, dstport: in0 }
|
||||||
- { srcblk: ep13, srcport: out0, dstblk: replay0, dstport: in_5 }
|
- { srcblk: ep13, srcport: out0, dstblk: replay1, dstport: in_1 }
|
||||||
- { srcblk: replay0, srcport: out_5, dstblk: ep13, dstport: in0 }
|
- { srcblk: replay1, srcport: out_1, dstblk: ep13, dstport: in0 }
|
||||||
- { srcblk: ep14, srcport: out0, dstblk: replay0, dstport: in_6 }
|
- { srcblk: ep14, srcport: out0, dstblk: replay1, dstport: in_2 }
|
||||||
- { srcblk: replay0, srcport: out_6, dstblk: ep14, dstport: in0 }
|
- { srcblk: replay1, srcport: out_2, dstblk: ep14, dstport: in0 }
|
||||||
- { srcblk: ep15, srcport: out0, dstblk: replay0, dstport: in_7 }
|
- { srcblk: ep15, srcport: out0, dstblk: replay1, dstport: in_3 }
|
||||||
- { srcblk: replay0, srcport: out_7, dstblk: ep15, dstport: in0 }
|
- { srcblk: replay1, srcport: out_3, dstblk: ep15, dstport: in0 }
|
||||||
#
|
#
|
||||||
# BSP Connections
|
# BSP Connections
|
||||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||||
@@ -202,7 +208,8 @@ connections:
|
|||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
|
- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
|
||||||
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
|
- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
|
||||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram0 }
|
||||||
|
- { srcblk: replay1, srcport: axi_ram, dstblk: _device_, dstport: dram1 }
|
||||||
|
|
||||||
# A list of all clock domain connections in design
|
# A list of all clock domain connections in design
|
||||||
# ------------------------------------------------
|
# ------------------------------------------------
|
||||||
@@ -215,3 +222,4 @@ clk_domains:
|
|||||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||||
|
- { srcblk: _device_, srcport: dram, dstblk: replay1, dstport: mem }
|
||||||
|
|||||||
@@ -23,11 +23,11 @@
|
|||||||
04c202c0
|
04c202c0
|
||||||
030004c3
|
030004c3
|
||||||
04c30300
|
04c30300
|
||||||
034004c4
|
03400500
|
||||||
04c40340
|
05000340
|
||||||
038004c5
|
03800501
|
||||||
04c50380
|
05010380
|
||||||
03c004c6
|
03c00502
|
||||||
04c603c0
|
050203c0
|
||||||
040004c7
|
04000503
|
||||||
04c70400
|
05030400
|
||||||
|
|||||||
@@ -36,12 +36,12 @@ module rfnoc_image_core #(
|
|||||||
input wire chdr_aclk,
|
input wire chdr_aclk,
|
||||||
input wire ctrl_aclk,
|
input wire ctrl_aclk,
|
||||||
input wire core_arst,
|
input wire core_arst,
|
||||||
|
input wire ce_clk,
|
||||||
input wire radio0_clk,
|
input wire radio0_clk,
|
||||||
input wire radio1_clk,
|
input wire radio1_clk,
|
||||||
input wire radio0_2x_clk,
|
input wire radio0_2x_clk,
|
||||||
input wire radio1_2x_clk,
|
input wire radio1_2x_clk,
|
||||||
input wire dram_clk,
|
input wire dram_clk,
|
||||||
input wire ce_clk,
|
|
||||||
// Basic
|
// Basic
|
||||||
input wire [ 15:0] device_id,
|
input wire [ 15:0] device_id,
|
||||||
|
|
||||||
@@ -87,52 +87,98 @@ module rfnoc_image_core #(
|
|||||||
output wire [1023:0] radio_tx_data_radio1,
|
output wire [1023:0] radio_tx_data_radio1,
|
||||||
input wire [ 31:0] radio_tx_stb_radio1,
|
input wire [ 31:0] radio_tx_stb_radio1,
|
||||||
output wire [ 31:0] radio_tx_running_radio1,
|
output wire [ 31:0] radio_tx_running_radio1,
|
||||||
// dram
|
// dram0
|
||||||
input wire [ 0:0] axi_rst,
|
input wire [ 0:0] dram0_axi_rst,
|
||||||
output wire [ 7:0] m_axi_awid,
|
output wire [ 7:0] dram0_m_axi_awid,
|
||||||
output wire [ 383:0] m_axi_awaddr,
|
output wire [ 383:0] dram0_m_axi_awaddr,
|
||||||
output wire [ 63:0] m_axi_awlen,
|
output wire [ 63:0] dram0_m_axi_awlen,
|
||||||
output wire [ 23:0] m_axi_awsize,
|
output wire [ 23:0] dram0_m_axi_awsize,
|
||||||
output wire [ 15:0] m_axi_awburst,
|
output wire [ 15:0] dram0_m_axi_awburst,
|
||||||
output wire [ 7:0] m_axi_awlock,
|
output wire [ 7:0] dram0_m_axi_awlock,
|
||||||
output wire [ 31:0] m_axi_awcache,
|
output wire [ 31:0] dram0_m_axi_awcache,
|
||||||
output wire [ 23:0] m_axi_awprot,
|
output wire [ 23:0] dram0_m_axi_awprot,
|
||||||
output wire [ 31:0] m_axi_awqos,
|
output wire [ 31:0] dram0_m_axi_awqos,
|
||||||
output wire [ 31:0] m_axi_awregion,
|
output wire [ 31:0] dram0_m_axi_awregion,
|
||||||
output wire [ 7:0] m_axi_awuser,
|
output wire [ 7:0] dram0_m_axi_awuser,
|
||||||
output wire [ 7:0] m_axi_awvalid,
|
output wire [ 7:0] dram0_m_axi_awvalid,
|
||||||
input wire [ 7:0] m_axi_awready,
|
input wire [ 7:0] dram0_m_axi_awready,
|
||||||
output wire [4191:0] m_axi_wdata,
|
output wire [4191:0] dram0_m_axi_wdata,
|
||||||
output wire [ 511:0] m_axi_wstrb,
|
output wire [ 511:0] dram0_m_axi_wstrb,
|
||||||
output wire [ 7:0] m_axi_wlast,
|
output wire [ 7:0] dram0_m_axi_wlast,
|
||||||
output wire [ 7:0] m_axi_wuser,
|
output wire [ 7:0] dram0_m_axi_wuser,
|
||||||
output wire [ 7:0] m_axi_wvalid,
|
output wire [ 7:0] dram0_m_axi_wvalid,
|
||||||
input wire [ 7:0] m_axi_wready,
|
input wire [ 7:0] dram0_m_axi_wready,
|
||||||
input wire [ 7:0] m_axi_bid,
|
input wire [ 7:0] dram0_m_axi_bid,
|
||||||
input wire [ 15:0] m_axi_bresp,
|
input wire [ 15:0] dram0_m_axi_bresp,
|
||||||
input wire [ 7:0] m_axi_buser,
|
input wire [ 7:0] dram0_m_axi_buser,
|
||||||
input wire [ 7:0] m_axi_bvalid,
|
input wire [ 7:0] dram0_m_axi_bvalid,
|
||||||
output wire [ 7:0] m_axi_bready,
|
output wire [ 7:0] dram0_m_axi_bready,
|
||||||
output wire [ 7:0] m_axi_arid,
|
output wire [ 7:0] dram0_m_axi_arid,
|
||||||
output wire [ 383:0] m_axi_araddr,
|
output wire [ 383:0] dram0_m_axi_araddr,
|
||||||
output wire [ 63:0] m_axi_arlen,
|
output wire [ 63:0] dram0_m_axi_arlen,
|
||||||
output wire [ 23:0] m_axi_arsize,
|
output wire [ 23:0] dram0_m_axi_arsize,
|
||||||
output wire [ 15:0] m_axi_arburst,
|
output wire [ 15:0] dram0_m_axi_arburst,
|
||||||
output wire [ 7:0] m_axi_arlock,
|
output wire [ 7:0] dram0_m_axi_arlock,
|
||||||
output wire [ 31:0] m_axi_arcache,
|
output wire [ 31:0] dram0_m_axi_arcache,
|
||||||
output wire [ 31:0] m_axi_arprot,
|
output wire [ 31:0] dram0_m_axi_arprot,
|
||||||
output wire [ 31:0] m_axi_arqos,
|
output wire [ 31:0] dram0_m_axi_arqos,
|
||||||
output wire [ 31:0] m_axi_arregion,
|
output wire [ 31:0] dram0_m_axi_arregion,
|
||||||
output wire [ 7:0] m_axi_aruser,
|
output wire [ 7:0] dram0_m_axi_aruser,
|
||||||
output wire [ 7:0] m_axi_arvalid,
|
output wire [ 7:0] dram0_m_axi_arvalid,
|
||||||
input wire [ 7:0] m_axi_arready,
|
input wire [ 7:0] dram0_m_axi_arready,
|
||||||
input wire [ 7:0] m_axi_rid,
|
input wire [ 7:0] dram0_m_axi_rid,
|
||||||
input wire [4191:0] m_axi_rdata,
|
input wire [4191:0] dram0_m_axi_rdata,
|
||||||
input wire [ 15:0] m_axi_rresp,
|
input wire [ 15:0] dram0_m_axi_rresp,
|
||||||
input wire [ 7:0] m_axi_rlast,
|
input wire [ 7:0] dram0_m_axi_rlast,
|
||||||
input wire [ 7:0] m_axi_ruser,
|
input wire [ 7:0] dram0_m_axi_ruser,
|
||||||
input wire [ 7:0] m_axi_rvalid,
|
input wire [ 7:0] dram0_m_axi_rvalid,
|
||||||
output wire [ 7:0] m_axi_rready,
|
output wire [ 7:0] dram0_m_axi_rready,
|
||||||
|
// dram1
|
||||||
|
input wire [ 0:0] dram1_axi_rst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_awaddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_awlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_awburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awcache,
|
||||||
|
output wire [ 23:0] dram1_m_axi_awprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_awregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_awvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_awready,
|
||||||
|
output wire [4191:0] dram1_m_axi_wdata,
|
||||||
|
output wire [ 511:0] dram1_m_axi_wstrb,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wlast,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wuser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_wvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_wready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bid,
|
||||||
|
input wire [ 15:0] dram1_m_axi_bresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_buser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_bvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_bready,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arid,
|
||||||
|
output wire [ 383:0] dram1_m_axi_araddr,
|
||||||
|
output wire [ 63:0] dram1_m_axi_arlen,
|
||||||
|
output wire [ 23:0] dram1_m_axi_arsize,
|
||||||
|
output wire [ 15:0] dram1_m_axi_arburst,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arlock,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arcache,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arprot,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arqos,
|
||||||
|
output wire [ 31:0] dram1_m_axi_arregion,
|
||||||
|
output wire [ 7:0] dram1_m_axi_aruser,
|
||||||
|
output wire [ 7:0] dram1_m_axi_arvalid,
|
||||||
|
input wire [ 7:0] dram1_m_axi_arready,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rid,
|
||||||
|
input wire [4191:0] dram1_m_axi_rdata,
|
||||||
|
input wire [ 15:0] dram1_m_axi_rresp,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rlast,
|
||||||
|
input wire [ 7:0] dram1_m_axi_ruser,
|
||||||
|
input wire [ 7:0] dram1_m_axi_rvalid,
|
||||||
|
output wire [ 7:0] dram1_m_axi_rready,
|
||||||
|
|
||||||
// Transport Adapters ///////////////
|
// Transport Adapters ///////////////
|
||||||
|
|
||||||
|
|||||||
+255
-129
@@ -421,9 +421,10 @@ module x4xx_core #(
|
|||||||
`define DRAM_W 64
|
`define DRAM_W 64
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
localparam DRAM_AXI_DWIDTH = `DRAM_W;
|
localparam ENABLE_DRAM = (`DRAM_CH > 0 && `DRAM_BANKS > 0);
|
||||||
localparam ENABLE_DRAM = (`DRAM_CH > 0);
|
localparam DRAM_AXI_DWIDTH = `DRAM_W;
|
||||||
localparam DRAM_NUM_PORTS = `DRAM_CH;
|
localparam DRAM_NUM_BANKS = ENABLE_DRAM ? `DRAM_BANKS : 1;
|
||||||
|
localparam DRAM_PORTS_PER_BANK = ENABLE_DRAM ? `DRAM_CH / DRAM_NUM_BANKS : 1;
|
||||||
|
|
||||||
wire dram0_ui_clk;
|
wire dram0_ui_clk;
|
||||||
wire dram0_ui_clk_sync_rst;
|
wire dram0_ui_clk_sync_rst;
|
||||||
@@ -432,50 +433,91 @@ module x4xx_core #(
|
|||||||
wire dram_rst = dram0_ui_clk_sync_rst;
|
wire dram_rst = dram0_ui_clk_sync_rst;
|
||||||
wire sys_rst = rfnoc_chdr_rst;
|
wire sys_rst = rfnoc_chdr_rst;
|
||||||
|
|
||||||
wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_araddr;
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_araddr;
|
||||||
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_arburst;
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arburst;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arcache;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arcache;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arid;
|
||||||
wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_arlen;
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlen;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arlock;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlock;
|
||||||
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arprot;
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arprot;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arqos;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arqos;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arready;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arready;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arregion;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arregion;
|
||||||
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arsize;
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arsize;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arvalid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arvalid;
|
||||||
wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_awaddr;
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awaddr;
|
||||||
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_awburst;
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awburst;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awcache;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awcache;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awid;
|
||||||
wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_awlen;
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlen;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awlock;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlock;
|
||||||
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awprot;
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awprot;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awqos;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awqos;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awready;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awready;
|
||||||
wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awregion;
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awregion;
|
||||||
wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awsize;
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awsize;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awvalid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awvalid;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bid;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bready;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bready;
|
||||||
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_bresp;
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bresp;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bvalid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bvalid;
|
||||||
wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_rdata;
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rdata;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rid;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rlast;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rlast;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rready;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rready;
|
||||||
wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_rresp;
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rresp;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rvalid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rvalid;
|
||||||
wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_wdata;
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wdata;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wlast;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wlast;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wready;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wready;
|
||||||
wire [DRAM_AXI_DWIDTH/8*DRAM_NUM_PORTS-1:0] dram_axi_wstrb;
|
wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wstrb;
|
||||||
wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wvalid;
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wvalid;
|
||||||
|
|
||||||
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_araddr;
|
||||||
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arburst;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arcache;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arid;
|
||||||
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlen;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlock;
|
||||||
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arprot;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arqos;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arready;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arregion;
|
||||||
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arsize;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arvalid;
|
||||||
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awaddr;
|
||||||
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awburst;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awcache;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awid;
|
||||||
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlen;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlock;
|
||||||
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awprot;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awqos;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awready;
|
||||||
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awregion;
|
||||||
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awsize;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awvalid;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bid;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bready;
|
||||||
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bresp;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bvalid;
|
||||||
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rdata;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rid;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rlast;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rready;
|
||||||
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rresp;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rvalid;
|
||||||
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wdata;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wlast;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wready;
|
||||||
|
wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wstrb;
|
||||||
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wvalid;
|
||||||
|
|
||||||
x4xx_dram #(
|
x4xx_dram #(
|
||||||
.ENABLE_DRAM (ENABLE_DRAM),
|
.ENABLE_DRAM (ENABLE_DRAM),
|
||||||
.AXI_DWIDTH (DRAM_AXI_DWIDTH),
|
.AXI_DWIDTH (DRAM_AXI_DWIDTH),
|
||||||
.NUM_PORTS (DRAM_NUM_PORTS)
|
.NUM_BANKS (DRAM_NUM_BANKS),
|
||||||
|
.PORTS_PER_BANK (DRAM_PORTS_PER_BANK)
|
||||||
) x4xx_dram_i (
|
) x4xx_dram_i (
|
||||||
.sys_rst (sys_rst),
|
.sys_rst (sys_rst),
|
||||||
.dram0_sys_clk_p (dram0_sys_clk_p),
|
.dram0_sys_clk_p (dram0_sys_clk_p),
|
||||||
@@ -517,45 +559,84 @@ module x4xx_core #(
|
|||||||
.dram_clk (dram_clk),
|
.dram_clk (dram_clk),
|
||||||
.dram_rst (dram_rst),
|
.dram_rst (dram_rst),
|
||||||
.dram_init_calib_complete (),
|
.dram_init_calib_complete (),
|
||||||
.dram_axi_araddr (dram_axi_araddr),
|
.dram0_axi_araddr (dram0_axi_araddr),
|
||||||
.dram_axi_arburst (dram_axi_arburst),
|
.dram0_axi_arburst (dram0_axi_arburst),
|
||||||
.dram_axi_arcache (dram_axi_arcache),
|
.dram0_axi_arcache (dram0_axi_arcache),
|
||||||
.dram_axi_arid (dram_axi_arid),
|
.dram0_axi_arid (dram0_axi_arid),
|
||||||
.dram_axi_arlen (dram_axi_arlen),
|
.dram0_axi_arlen (dram0_axi_arlen),
|
||||||
.dram_axi_arlock (dram_axi_arlock),
|
.dram0_axi_arlock (dram0_axi_arlock),
|
||||||
.dram_axi_arprot (dram_axi_arprot),
|
.dram0_axi_arprot (dram0_axi_arprot),
|
||||||
.dram_axi_arqos (dram_axi_arqos),
|
.dram0_axi_arqos (dram0_axi_arqos),
|
||||||
.dram_axi_arready (dram_axi_arready),
|
.dram0_axi_arready (dram0_axi_arready),
|
||||||
.dram_axi_arregion (dram_axi_arregion),
|
.dram0_axi_arregion (dram0_axi_arregion),
|
||||||
.dram_axi_arsize (dram_axi_arsize),
|
.dram0_axi_arsize (dram0_axi_arsize),
|
||||||
.dram_axi_arvalid (dram_axi_arvalid),
|
.dram0_axi_arvalid (dram0_axi_arvalid),
|
||||||
.dram_axi_awaddr (dram_axi_awaddr),
|
.dram0_axi_awaddr (dram0_axi_awaddr),
|
||||||
.dram_axi_awburst (dram_axi_awburst),
|
.dram0_axi_awburst (dram0_axi_awburst),
|
||||||
.dram_axi_awcache (dram_axi_awcache),
|
.dram0_axi_awcache (dram0_axi_awcache),
|
||||||
.dram_axi_awid (dram_axi_awid),
|
.dram0_axi_awid (dram0_axi_awid),
|
||||||
.dram_axi_awlen (dram_axi_awlen),
|
.dram0_axi_awlen (dram0_axi_awlen),
|
||||||
.dram_axi_awlock (dram_axi_awlock),
|
.dram0_axi_awlock (dram0_axi_awlock),
|
||||||
.dram_axi_awprot (dram_axi_awprot),
|
.dram0_axi_awprot (dram0_axi_awprot),
|
||||||
.dram_axi_awqos (dram_axi_awqos),
|
.dram0_axi_awqos (dram0_axi_awqos),
|
||||||
.dram_axi_awready (dram_axi_awready),
|
.dram0_axi_awready (dram0_axi_awready),
|
||||||
.dram_axi_awregion (dram_axi_awregion),
|
.dram0_axi_awregion (dram0_axi_awregion),
|
||||||
.dram_axi_awsize (dram_axi_awsize),
|
.dram0_axi_awsize (dram0_axi_awsize),
|
||||||
.dram_axi_awvalid (dram_axi_awvalid),
|
.dram0_axi_awvalid (dram0_axi_awvalid),
|
||||||
.dram_axi_bid (dram_axi_bid),
|
.dram0_axi_bid (dram0_axi_bid),
|
||||||
.dram_axi_bready (dram_axi_bready),
|
.dram0_axi_bready (dram0_axi_bready),
|
||||||
.dram_axi_bresp (dram_axi_bresp),
|
.dram0_axi_bresp (dram0_axi_bresp),
|
||||||
.dram_axi_bvalid (dram_axi_bvalid),
|
.dram0_axi_bvalid (dram0_axi_bvalid),
|
||||||
.dram_axi_rdata (dram_axi_rdata),
|
.dram0_axi_rdata (dram0_axi_rdata),
|
||||||
.dram_axi_rid (dram_axi_rid),
|
.dram0_axi_rid (dram0_axi_rid),
|
||||||
.dram_axi_rlast (dram_axi_rlast),
|
.dram0_axi_rlast (dram0_axi_rlast),
|
||||||
.dram_axi_rready (dram_axi_rready),
|
.dram0_axi_rready (dram0_axi_rready),
|
||||||
.dram_axi_rresp (dram_axi_rresp),
|
.dram0_axi_rresp (dram0_axi_rresp),
|
||||||
.dram_axi_rvalid (dram_axi_rvalid),
|
.dram0_axi_rvalid (dram0_axi_rvalid),
|
||||||
.dram_axi_wdata (dram_axi_wdata),
|
.dram0_axi_wdata (dram0_axi_wdata),
|
||||||
.dram_axi_wlast (dram_axi_wlast),
|
.dram0_axi_wlast (dram0_axi_wlast),
|
||||||
.dram_axi_wready (dram_axi_wready),
|
.dram0_axi_wready (dram0_axi_wready),
|
||||||
.dram_axi_wstrb (dram_axi_wstrb),
|
.dram0_axi_wstrb (dram0_axi_wstrb),
|
||||||
.dram_axi_wvalid (dram_axi_wvalid)
|
.dram0_axi_wvalid (dram0_axi_wvalid),
|
||||||
|
.dram1_axi_araddr (dram1_axi_araddr),
|
||||||
|
.dram1_axi_arburst (dram1_axi_arburst),
|
||||||
|
.dram1_axi_arcache (dram1_axi_arcache),
|
||||||
|
.dram1_axi_arid (dram1_axi_arid),
|
||||||
|
.dram1_axi_arlen (dram1_axi_arlen),
|
||||||
|
.dram1_axi_arlock (dram1_axi_arlock),
|
||||||
|
.dram1_axi_arprot (dram1_axi_arprot),
|
||||||
|
.dram1_axi_arqos (dram1_axi_arqos),
|
||||||
|
.dram1_axi_arready (dram1_axi_arready),
|
||||||
|
.dram1_axi_arregion (dram1_axi_arregion),
|
||||||
|
.dram1_axi_arsize (dram1_axi_arsize),
|
||||||
|
.dram1_axi_arvalid (dram1_axi_arvalid),
|
||||||
|
.dram1_axi_awaddr (dram1_axi_awaddr),
|
||||||
|
.dram1_axi_awburst (dram1_axi_awburst),
|
||||||
|
.dram1_axi_awcache (dram1_axi_awcache),
|
||||||
|
.dram1_axi_awid (dram1_axi_awid),
|
||||||
|
.dram1_axi_awlen (dram1_axi_awlen),
|
||||||
|
.dram1_axi_awlock (dram1_axi_awlock),
|
||||||
|
.dram1_axi_awprot (dram1_axi_awprot),
|
||||||
|
.dram1_axi_awqos (dram1_axi_awqos),
|
||||||
|
.dram1_axi_awready (dram1_axi_awready),
|
||||||
|
.dram1_axi_awregion (dram1_axi_awregion),
|
||||||
|
.dram1_axi_awsize (dram1_axi_awsize),
|
||||||
|
.dram1_axi_awvalid (dram1_axi_awvalid),
|
||||||
|
.dram1_axi_bid (dram1_axi_bid),
|
||||||
|
.dram1_axi_bready (dram1_axi_bready),
|
||||||
|
.dram1_axi_bresp (dram1_axi_bresp),
|
||||||
|
.dram1_axi_bvalid (dram1_axi_bvalid),
|
||||||
|
.dram1_axi_rdata (dram1_axi_rdata),
|
||||||
|
.dram1_axi_rid (dram1_axi_rid),
|
||||||
|
.dram1_axi_rlast (dram1_axi_rlast),
|
||||||
|
.dram1_axi_rready (dram1_axi_rready),
|
||||||
|
.dram1_axi_rresp (dram1_axi_rresp),
|
||||||
|
.dram1_axi_rvalid (dram1_axi_rvalid),
|
||||||
|
.dram1_axi_wdata (dram1_axi_wdata),
|
||||||
|
.dram1_axi_wlast (dram1_axi_wlast),
|
||||||
|
.dram1_axi_wready (dram1_axi_wready),
|
||||||
|
.dram1_axi_wstrb (dram1_axi_wstrb),
|
||||||
|
.dram1_axi_wvalid (dram1_axi_wvalid)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -662,51 +743,96 @@ module x4xx_core #(
|
|||||||
`else
|
`else
|
||||||
.radio_time (radio_time[0*64+:64]),
|
.radio_time (radio_time[0*64+:64]),
|
||||||
`endif
|
`endif
|
||||||
.axi_rst (dram_rst),
|
.dram0_axi_rst (dram_rst),
|
||||||
.m_axi_awid (dram_axi_awid),
|
.dram0_m_axi_awid (dram0_axi_awid),
|
||||||
.m_axi_awaddr (dram_axi_awaddr),
|
.dram0_m_axi_awaddr (dram0_axi_awaddr),
|
||||||
.m_axi_awlen (dram_axi_awlen),
|
.dram0_m_axi_awlen (dram0_axi_awlen),
|
||||||
.m_axi_awsize (dram_axi_awsize),
|
.dram0_m_axi_awsize (dram0_axi_awsize),
|
||||||
.m_axi_awburst (dram_axi_awburst),
|
.dram0_m_axi_awburst (dram0_axi_awburst),
|
||||||
.m_axi_awlock (dram_axi_awlock),
|
.dram0_m_axi_awlock (dram0_axi_awlock),
|
||||||
.m_axi_awcache (dram_axi_awcache),
|
.dram0_m_axi_awcache (dram0_axi_awcache),
|
||||||
.m_axi_awprot (dram_axi_awprot),
|
.dram0_m_axi_awprot (dram0_axi_awprot),
|
||||||
.m_axi_awqos (dram_axi_awqos),
|
.dram0_m_axi_awqos (dram0_axi_awqos),
|
||||||
.m_axi_awregion (dram_axi_awregion),
|
.dram0_m_axi_awregion (dram0_axi_awregion),
|
||||||
.m_axi_awuser (),
|
.dram0_m_axi_awuser (),
|
||||||
.m_axi_awvalid (dram_axi_awvalid),
|
.dram0_m_axi_awvalid (dram0_axi_awvalid),
|
||||||
.m_axi_awready (dram_axi_awready),
|
.dram0_m_axi_awready (dram0_axi_awready),
|
||||||
.m_axi_wdata (dram_axi_wdata),
|
.dram0_m_axi_wdata (dram0_axi_wdata),
|
||||||
.m_axi_wstrb (dram_axi_wstrb),
|
.dram0_m_axi_wstrb (dram0_axi_wstrb),
|
||||||
.m_axi_wlast (dram_axi_wlast),
|
.dram0_m_axi_wlast (dram0_axi_wlast),
|
||||||
.m_axi_wuser (),
|
.dram0_m_axi_wuser (),
|
||||||
.m_axi_wvalid (dram_axi_wvalid),
|
.dram0_m_axi_wvalid (dram0_axi_wvalid),
|
||||||
.m_axi_wready (dram_axi_wready),
|
.dram0_m_axi_wready (dram0_axi_wready),
|
||||||
.m_axi_bid (dram_axi_bid),
|
.dram0_m_axi_bid (dram0_axi_bid),
|
||||||
.m_axi_bresp (dram_axi_bresp),
|
.dram0_m_axi_bresp (dram0_axi_bresp),
|
||||||
.m_axi_buser (0),
|
.dram0_m_axi_buser (0),
|
||||||
.m_axi_bvalid (dram_axi_bvalid),
|
.dram0_m_axi_bvalid (dram0_axi_bvalid),
|
||||||
.m_axi_bready (dram_axi_bready),
|
.dram0_m_axi_bready (dram0_axi_bready),
|
||||||
.m_axi_arid (dram_axi_arid),
|
.dram0_m_axi_arid (dram0_axi_arid),
|
||||||
.m_axi_araddr (dram_axi_araddr),
|
.dram0_m_axi_araddr (dram0_axi_araddr),
|
||||||
.m_axi_arlen (dram_axi_arlen),
|
.dram0_m_axi_arlen (dram0_axi_arlen),
|
||||||
.m_axi_arsize (dram_axi_arsize),
|
.dram0_m_axi_arsize (dram0_axi_arsize),
|
||||||
.m_axi_arburst (dram_axi_arburst),
|
.dram0_m_axi_arburst (dram0_axi_arburst),
|
||||||
.m_axi_arlock (dram_axi_arlock),
|
.dram0_m_axi_arlock (dram0_axi_arlock),
|
||||||
.m_axi_arcache (dram_axi_arcache),
|
.dram0_m_axi_arcache (dram0_axi_arcache),
|
||||||
.m_axi_arprot (dram_axi_arprot),
|
.dram0_m_axi_arprot (dram0_axi_arprot),
|
||||||
.m_axi_arqos (dram_axi_arqos),
|
.dram0_m_axi_arqos (dram0_axi_arqos),
|
||||||
.m_axi_arregion (dram_axi_arregion),
|
.dram0_m_axi_arregion (dram0_axi_arregion),
|
||||||
.m_axi_aruser (),
|
.dram0_m_axi_aruser (),
|
||||||
.m_axi_arvalid (dram_axi_arvalid),
|
.dram0_m_axi_arvalid (dram0_axi_arvalid),
|
||||||
.m_axi_arready (dram_axi_arready),
|
.dram0_m_axi_arready (dram0_axi_arready),
|
||||||
.m_axi_rid (dram_axi_rid),
|
.dram0_m_axi_rid (dram0_axi_rid),
|
||||||
.m_axi_rdata (dram_axi_rdata),
|
.dram0_m_axi_rdata (dram0_axi_rdata),
|
||||||
.m_axi_rresp (dram_axi_rresp),
|
.dram0_m_axi_rresp (dram0_axi_rresp),
|
||||||
.m_axi_rlast (dram_axi_rlast),
|
.dram0_m_axi_rlast (dram0_axi_rlast),
|
||||||
.m_axi_ruser (0),
|
.dram0_m_axi_ruser (0),
|
||||||
.m_axi_rvalid (dram_axi_rvalid),
|
.dram0_m_axi_rvalid (dram0_axi_rvalid),
|
||||||
.m_axi_rready (dram_axi_rready),
|
.dram0_m_axi_rready (dram0_axi_rready),
|
||||||
|
.dram1_axi_rst (dram_rst),
|
||||||
|
.dram1_m_axi_awid (dram1_axi_awid),
|
||||||
|
.dram1_m_axi_awaddr (dram1_axi_awaddr),
|
||||||
|
.dram1_m_axi_awlen (dram1_axi_awlen),
|
||||||
|
.dram1_m_axi_awsize (dram1_axi_awsize),
|
||||||
|
.dram1_m_axi_awburst (dram1_axi_awburst),
|
||||||
|
.dram1_m_axi_awlock (dram1_axi_awlock),
|
||||||
|
.dram1_m_axi_awcache (dram1_axi_awcache),
|
||||||
|
.dram1_m_axi_awprot (dram1_axi_awprot),
|
||||||
|
.dram1_m_axi_awqos (dram1_axi_awqos),
|
||||||
|
.dram1_m_axi_awregion (dram1_axi_awregion),
|
||||||
|
.dram1_m_axi_awuser (),
|
||||||
|
.dram1_m_axi_awvalid (dram1_axi_awvalid),
|
||||||
|
.dram1_m_axi_awready (dram1_axi_awready),
|
||||||
|
.dram1_m_axi_wdata (dram1_axi_wdata),
|
||||||
|
.dram1_m_axi_wstrb (dram1_axi_wstrb),
|
||||||
|
.dram1_m_axi_wlast (dram1_axi_wlast),
|
||||||
|
.dram1_m_axi_wuser (),
|
||||||
|
.dram1_m_axi_wvalid (dram1_axi_wvalid),
|
||||||
|
.dram1_m_axi_wready (dram1_axi_wready),
|
||||||
|
.dram1_m_axi_bid (dram1_axi_bid),
|
||||||
|
.dram1_m_axi_bresp (dram1_axi_bresp),
|
||||||
|
.dram1_m_axi_buser (0),
|
||||||
|
.dram1_m_axi_bvalid (dram1_axi_bvalid),
|
||||||
|
.dram1_m_axi_bready (dram1_axi_bready),
|
||||||
|
.dram1_m_axi_arid (dram1_axi_arid),
|
||||||
|
.dram1_m_axi_araddr (dram1_axi_araddr),
|
||||||
|
.dram1_m_axi_arlen (dram1_axi_arlen),
|
||||||
|
.dram1_m_axi_arsize (dram1_axi_arsize),
|
||||||
|
.dram1_m_axi_arburst (dram1_axi_arburst),
|
||||||
|
.dram1_m_axi_arlock (dram1_axi_arlock),
|
||||||
|
.dram1_m_axi_arcache (dram1_axi_arcache),
|
||||||
|
.dram1_m_axi_arprot (dram1_axi_arprot),
|
||||||
|
.dram1_m_axi_arqos (dram1_axi_arqos),
|
||||||
|
.dram1_m_axi_arregion (dram1_axi_arregion),
|
||||||
|
.dram1_m_axi_aruser (),
|
||||||
|
.dram1_m_axi_arvalid (dram1_axi_arvalid),
|
||||||
|
.dram1_m_axi_arready (dram1_axi_arready),
|
||||||
|
.dram1_m_axi_rid (dram1_axi_rid),
|
||||||
|
.dram1_m_axi_rdata (dram1_axi_rdata),
|
||||||
|
.dram1_m_axi_rresp (dram1_axi_rresp),
|
||||||
|
.dram1_m_axi_rlast (dram1_axi_rlast),
|
||||||
|
.dram1_m_axi_ruser (0),
|
||||||
|
.dram1_m_axi_rvalid (dram1_axi_rvalid),
|
||||||
|
.dram1_m_axi_rready (dram1_axi_rready),
|
||||||
.s_eth0_tdata (e2v_tdata [0*ENET_W +: ENET0_W]),
|
.s_eth0_tdata (e2v_tdata [0*ENET_W +: ENET0_W]),
|
||||||
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
|
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
|
||||||
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
|
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
|
||||||
|
|||||||
+1767
-1699
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user