Wade Fife
e87c82cc74
This updates the RFNoC image cores to separate the two DRAM banks on X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM banks shared the same DRAM port, named "dram", which created some confusion. The Replay block has also been duplicated in the bitstreams that use both banks, so we now have one Replay block per bank. Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
887 lines
41 KiB
Verilog
887 lines
41 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0
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//
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// Module: x4xx_core
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//
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// Description:
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//
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// This module contains the core infrastructure for RFNoC, such as the
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// motherboard register, timekeeper, and RFNoC image core.
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//
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// Parameters:
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//
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// NUM_DBOARDS : Number of daughter boards
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// REG_DWIDTH : Width of the AXI4-Lite data bus (must be 32 or 64)
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// REG_AWIDTH : Width of the address bus
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// CHDR_CLK_RATE : rfnoc_chdr_clk rate in Hz
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// NUM_CHANNELS : Total number of channels
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// NUM_CH_PER_DB : Number of channels per daughterboard and radio core
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// CHDR_W : CHDR width used by RFNoC
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// DMA_W : Width of the DMA port interface
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// NET_CHDR_W : CHDR width used by the network interface ports
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// ENET_W : Width of the Ethernet buses (each port may have a unique
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// width, but all signals have equal width for simplicity).
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// ENET_WIDTHS : Actual width of each Ethernet port's interface. This is
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// a packed array of 32-bit integers with port 0 in the
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// right-most position.
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// MTU : Log2 of maximum transmission unit in CHDR_W sized words
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// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
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// RADIO_SPC : Number of samples per radio clock cycle
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// NUM_TIMEKEEPERS : Number of timekeepers
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// RF_BANDWIDTH : RF bandwidth of each radio channel
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//
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module x4xx_core #(
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parameter NUM_DBOARDS = 2,
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parameter REG_DWIDTH = 32,
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parameter REG_AWIDTH = 32,
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parameter CHDR_CLK_RATE = 200000000,
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parameter NUM_CH_PER_DB = 2,
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parameter NUM_CHANNELS = NUM_CH_PER_DB*NUM_DBOARDS,
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parameter CHDR_W = 64,
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parameter DMA_W = 64,
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parameter NET_CHDR_W = 64,
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parameter [ 31:0] ENET_W = 64,
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parameter [32*8-1:0] ENET_WIDTHS = {8{ENET_W}},
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parameter MTU = $clog2(8192 / (CHDR_W/8)),
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parameter RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter RADIO_SPC = 1,
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parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
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parameter RF_BANDWIDTH = 200
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) (
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// Clocks and resets
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input wire [NUM_DBOARDS-1:0] radio_clk,
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input wire [NUM_DBOARDS-1:0] radio_rst,
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input wire [NUM_DBOARDS-1:0] radio_clk_2x,
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input wire rfnoc_chdr_clk,
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input wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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input wire rfnoc_ctrl_rst,
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input wire ce_clk,
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// DRAM Bank 0
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input wire dram0_sys_clk_p,
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input wire dram0_sys_clk_n,
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output wire dram0_ck_t,
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output wire dram0_ck_c,
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output wire dram0_cs_n,
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output wire dram0_act_n,
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output wire [ 16:0] dram0_adr,
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output wire [ 1:0] dram0_ba,
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output wire dram0_bg,
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output wire dram0_cke,
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output wire dram0_odt,
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output wire dram0_reset_n,
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inout wire [ 7:0] dram0_dm_dbi_n,
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inout wire [ 63:0] dram0_dq,
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inout wire [ 7:0] dram0_dqs_t,
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inout wire [ 7:0] dram0_dqs_c,
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// DRAM Bank 1
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input wire dram1_sys_clk_p,
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input wire dram1_sys_clk_n,
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output wire dram1_ck_t,
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output wire dram1_ck_c,
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output wire dram1_cs_n,
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output wire dram1_act_n,
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output wire [ 16:0] dram1_adr,
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output wire [ 1:0] dram1_ba,
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output wire dram1_bg,
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output wire dram1_cke,
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output wire dram1_odt,
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output wire dram1_reset_n,
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inout wire [ 7:0] dram1_dm_dbi_n,
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inout wire [ 63:0] dram1_dq,
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inout wire [ 7:0] dram1_dqs_t,
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inout wire [ 7:0] dram1_dqs_c,
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// AXI-Lite interface (for motherboard registers)
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input s_axi_aclk,
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input s_axi_aresetn,
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input [ REG_AWIDTH-1:0] s_axi_awaddr,
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input s_axi_awvalid,
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output s_axi_awready,
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input [ REG_DWIDTH-1:0] s_axi_wdata,
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input [REG_DWIDTH/8-1:0] s_axi_wstrb,
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input s_axi_wvalid,
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output s_axi_wready,
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output [ 1:0] s_axi_bresp,
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output s_axi_bvalid,
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input s_axi_bready,
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input [ REG_AWIDTH-1:0] s_axi_araddr,
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input s_axi_arvalid,
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output s_axi_arready,
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output [ REG_DWIDTH-1:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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output s_axi_rvalid,
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input s_axi_rready,
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// PPS and Clock Control
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input [ 1:0] pps_radioclk,
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output [ 1:0] pps_select,
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output [ 1:0] trig_io_select,
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output pll_sync_trigger,
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output [ 7:0] pll_sync_delay,
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input pll_sync_done,
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output [ 7:0] pps_brc_delay,
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output [25:0] pps_prc_delay,
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output [ 4:0] prc_rc0_divider,
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output [ 4:0] prc_rc1_divider,
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output pps_rc_enabled,
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// Radio Data
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input [32*RADIO_SPC*NUM_CHANNELS-1:0] rx_data,
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input [ NUM_CHANNELS-1:0] rx_stb,
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output [ NUM_CHANNELS-1:0] rx_running,
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//
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output [32*RADIO_SPC*NUM_CHANNELS-1:0] tx_data,
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input [ NUM_CHANNELS-1:0] tx_stb,
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output [ NUM_CHANNELS-1:0] tx_running,
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// DMA
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output [DMA_W-1:0] dmao_tdata,
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output dmao_tlast,
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output dmao_tvalid,
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input dmao_tready,
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input [DMA_W-1:0] dmai_tdata,
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input dmai_tlast,
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input dmai_tvalid,
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output dmai_tready,
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// e2v (Ethernet to CHDR)
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output [ENET_W*8-1:0] v2e_tdata,
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output [ 8-1:0] v2e_tvalid,
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output [ 8-1:0] v2e_tlast,
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input [ 8-1:0] v2e_tready,
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// v2e (CHDR to Ethernet)
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input [ENET_W*8-1:0] e2v_tdata,
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input [ 8-1:0] e2v_tlast,
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input [ 8-1:0] e2v_tvalid,
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output [ 8-1:0] e2v_tready,
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// GPIO to DIO board (Domain: rfnoc_ctrl_clk)
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output wire [11:0] gpio_en_a,
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output wire [11:0] gpio_en_b,
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// GPIO to DIO board (async)
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input wire [11:0] gpio_in_a,
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input wire [11:0] gpio_in_b,
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output wire [11:0] gpio_out_a,
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output wire [11:0] gpio_out_b,
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// PS GPIO Control
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input wire [11:0] ps_gpio_out_a,
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output wire [11:0] ps_gpio_in_a,
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input wire [11:0] ps_gpio_ddr_a,
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input wire [11:0] ps_gpio_out_b,
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output wire [11:0] ps_gpio_in_b,
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input wire [11:0] ps_gpio_ddr_b,
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// Misc
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input [31:0] qsfp_port_0_0_info,
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input [31:0] qsfp_port_0_1_info,
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input [31:0] qsfp_port_0_2_info,
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input [31:0] qsfp_port_0_3_info,
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input [31:0] qsfp_port_1_0_info,
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input [31:0] qsfp_port_1_1_info,
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input [31:0] qsfp_port_1_2_info,
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input [31:0] qsfp_port_1_3_info,
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output [15:0] device_id,
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output mfg_test_en_fabric_clk,
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output mfg_test_en_gty_rcv_clk,
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input fpga_aux_ref,
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// Radio Control Ports
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output wire [64*NUM_TIMEKEEPERS-1:0] radio_time,
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output wire [ NUM_TIMEKEEPERS-1:0] radio_time_stb,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_wr,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_rd,
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output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_radio_req_addr,
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output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_req_data,
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input wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_ack,
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input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_status,
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input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_data,
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// RF Reset Control
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output wire start_nco_reset,
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input wire nco_reset_done,
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output wire adc_reset_pulse,
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output wire dac_reset_pulse,
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// Version (Constant)
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// Each component consists of a 96-bit vector (refer to versioning_utils.vh)
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input wire [64*96-1:0] version_info
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);
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//---------------------------------------------------------------------------
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// AXI-Lite to CtrlPort Bridge
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//---------------------------------------------------------------------------
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wire [19:0] ctrlport_req_addr;
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wire [ 3:0] ctrlport_req_byte_en;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_req_has_time;
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wire [ 9:0] ctrlport_req_portid;
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wire ctrlport_req_rd;
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wire [15:0] ctrlport_req_rem_epid;
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wire [ 9:0] ctrlport_req_rem_portid;
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wire [63:0] ctrlport_req_time;
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wire ctrlport_req_wr;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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wire [ 1:0] ctrlport_resp_status;
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`include "../../lib/rfnoc/core/ctrlport.vh"
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axil_ctrlport_master #(
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.TIMEOUT (10 ),
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.AXI_AWIDTH (REG_AWIDTH ),
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.CTRLPORT_AWIDTH(CTRLPORT_ADDR_W)
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) axil_ctrlport_master_i (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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.m_ctrlport_req_wr (ctrlport_req_wr),
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.m_ctrlport_req_rd (ctrlport_req_rd),
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.m_ctrlport_req_addr (ctrlport_req_addr),
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.m_ctrlport_req_portid (ctrlport_req_portid),
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.m_ctrlport_req_rem_epid (ctrlport_req_rem_epid),
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.m_ctrlport_req_rem_portid (ctrlport_req_rem_portid),
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.m_ctrlport_req_data (ctrlport_req_data),
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.m_ctrlport_req_byte_en (ctrlport_req_byte_en),
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.m_ctrlport_req_has_time (ctrlport_req_has_time),
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.m_ctrlport_req_time (ctrlport_req_time),
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.m_ctrlport_resp_ack (ctrlport_resp_ack),
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.m_ctrlport_resp_status (ctrlport_resp_status),
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.m_ctrlport_resp_data (ctrlport_resp_data)
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);
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//---------------------------------------------------------------------------
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// Common Components
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//---------------------------------------------------------------------------
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wire ctrlport_rst;
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reset_sync reset_sync_ctrlport (
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.clk (s_axi_aclk),
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.reset_in (~s_axi_aresetn),
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.reset_out (ctrlport_rst)
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);
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_wr;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] ctrlport_radio_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_req_data;
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wire [ 4*NUM_DBOARDS-1:0] ctrlport_radio_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] ctrlport_radio_req_time;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data;
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x4xx_core_common #(
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.CHDR_CLK_RATE (CHDR_CLK_RATE),
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.CHDR_W (NET_CHDR_W),
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.RFNOC_PROTOVER (RFNOC_PROTOVER),
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.NUM_DBOARDS (NUM_DBOARDS),
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.NUM_CH_PER_DB (NUM_CH_PER_DB),
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.NUM_TIMEKEEPERS (NUM_TIMEKEEPERS),
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.PCIE_PRESENT (0)
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) x4xx_core_common_i (
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.radio_clk (radio_clk),
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.radio_clk_2x (radio_clk_2x),
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.radio_rst (radio_rst),
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.ctrlport_clk (s_axi_aclk),
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.ctrlport_rst (ctrlport_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_portid (ctrlport_req_portid),
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.s_ctrlport_req_rem_epid (ctrlport_req_rem_epid),
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.s_ctrlport_req_rem_portid (ctrlport_req_rem_portid),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_byte_en (ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (ctrlport_req_has_time),
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.s_ctrlport_req_time (ctrlport_req_time),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_status (ctrlport_resp_status),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.pps_radioclk (pps_radioclk),
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.pps_select (pps_select),
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.trig_io_select (trig_io_select),
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.pll_sync_trigger (pll_sync_trigger),
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.pll_sync_delay (pll_sync_delay),
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.pll_sync_done (pll_sync_done),
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.pps_brc_delay (pps_brc_delay),
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.pps_prc_delay (pps_prc_delay),
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.prc_rc0_divider (prc_rc0_divider),
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.prc_rc1_divider (prc_rc1_divider),
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.pps_rc_enabled (pps_rc_enabled),
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.radio_spc (RADIO_SPC),
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.radio_time (radio_time),
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.sample_rx_stb (radio_time_stb),
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.time_ignore_bits ($clog2(RADIO_SPC)),
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.gpio_in_a (gpio_in_a),
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.gpio_in_b (gpio_in_b),
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.gpio_out_a (gpio_out_a),
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.gpio_out_b (gpio_out_b),
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.gpio_en_a (gpio_en_a),
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.gpio_en_b (gpio_en_b),
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.gpio_in_fabric_a (),
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.gpio_in_fabric_b (),
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.gpio_out_fabric_a (12'b0),
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.gpio_out_fabric_b (12'b0),
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.ps_gpio_out_a (ps_gpio_out_a),
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.ps_gpio_in_a (ps_gpio_in_a),
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.ps_gpio_ddr_a (ps_gpio_ddr_a),
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.ps_gpio_out_b (ps_gpio_out_b),
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.ps_gpio_in_b (ps_gpio_in_b),
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.ps_gpio_ddr_b (ps_gpio_ddr_b),
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.s_radio_ctrlport_req_wr (ctrlport_radio_req_wr),
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.s_radio_ctrlport_req_rd (ctrlport_radio_req_rd),
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.s_radio_ctrlport_req_addr (ctrlport_radio_req_addr),
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.s_radio_ctrlport_req_data (ctrlport_radio_req_data),
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.s_radio_ctrlport_req_byte_en (ctrlport_radio_req_byte_en),
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.s_radio_ctrlport_req_has_time (ctrlport_radio_req_has_time),
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.s_radio_ctrlport_req_time (ctrlport_radio_req_time),
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.s_radio_ctrlport_resp_ack (ctrlport_radio_resp_ack),
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.s_radio_ctrlport_resp_status (ctrlport_radio_resp_status),
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.s_radio_ctrlport_resp_data (ctrlport_radio_resp_data),
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.m_radio_ctrlport_req_wr (m_ctrlport_radio_req_wr),
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.m_radio_ctrlport_req_rd (m_ctrlport_radio_req_rd),
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.m_radio_ctrlport_req_addr (m_ctrlport_radio_req_addr),
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.m_radio_ctrlport_req_data (m_ctrlport_radio_req_data),
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.m_radio_ctrlport_resp_ack (m_ctrlport_radio_resp_ack),
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.m_radio_ctrlport_resp_status (m_ctrlport_radio_resp_status),
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.m_radio_ctrlport_resp_data (m_ctrlport_radio_resp_data),
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.start_nco_reset (start_nco_reset),
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.nco_reset_done (nco_reset_done),
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.adc_reset_pulse (adc_reset_pulse),
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.dac_reset_pulse (dac_reset_pulse),
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.tx_running (tx_running),
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.rx_running (rx_running),
|
|
.qsfp_port_0_0_info (qsfp_port_0_0_info),
|
|
.qsfp_port_0_1_info (qsfp_port_0_1_info),
|
|
.qsfp_port_0_2_info (qsfp_port_0_2_info),
|
|
.qsfp_port_0_3_info (qsfp_port_0_3_info),
|
|
.qsfp_port_1_0_info (qsfp_port_1_0_info),
|
|
.qsfp_port_1_1_info (qsfp_port_1_1_info),
|
|
.qsfp_port_1_2_info (qsfp_port_1_2_info),
|
|
.qsfp_port_1_3_info (qsfp_port_1_3_info),
|
|
.device_id (device_id),
|
|
.mfg_test_en_fabric_clk (mfg_test_en_fabric_clk),
|
|
.mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk),
|
|
.fpga_aux_ref (fpga_aux_ref),
|
|
.version_info (version_info)
|
|
);
|
|
|
|
// Provide information for ctrlport timed commands
|
|
genvar tk_i;
|
|
generate
|
|
for (tk_i = 0; tk_i < NUM_TIMEKEEPERS; tk_i = tk_i + 1) begin : gen_time_stb
|
|
assign radio_time_stb[tk_i] = rx_stb[tk_i*NUM_CH_PER_DB];
|
|
end
|
|
endgenerate
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// DRAM
|
|
//---------------------------------------------------------------------------
|
|
|
|
`ifndef DRAM_CH
|
|
`define DRAM_CH 0
|
|
`endif
|
|
`ifndef DRAM_W
|
|
`define DRAM_W 64
|
|
`endif
|
|
|
|
localparam ENABLE_DRAM = (`DRAM_CH > 0 && `DRAM_BANKS > 0);
|
|
localparam DRAM_AXI_DWIDTH = `DRAM_W;
|
|
localparam DRAM_NUM_BANKS = ENABLE_DRAM ? `DRAM_BANKS : 1;
|
|
localparam DRAM_PORTS_PER_BANK = ENABLE_DRAM ? `DRAM_CH / DRAM_NUM_BANKS : 1;
|
|
|
|
wire dram0_ui_clk;
|
|
wire dram0_ui_clk_sync_rst;
|
|
|
|
wire dram_clk = dram0_ui_clk;
|
|
wire dram_rst = dram0_ui_clk_sync_rst;
|
|
wire sys_rst = rfnoc_chdr_rst;
|
|
|
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_araddr;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arburst;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arcache;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arid;
|
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlen;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlock;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arprot;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arqos;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arready;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arregion;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arsize;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arvalid;
|
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awaddr;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awburst;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awcache;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awid;
|
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlen;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlock;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awprot;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awqos;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awready;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awregion;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awsize;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awvalid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bready;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bresp;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bvalid;
|
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rdata;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rlast;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rready;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rresp;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rvalid;
|
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wdata;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wlast;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wready;
|
|
wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wstrb;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wvalid;
|
|
|
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_araddr;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arburst;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arcache;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arid;
|
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlen;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlock;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arprot;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arqos;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arready;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arregion;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arsize;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arvalid;
|
|
wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awaddr;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awburst;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awcache;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awid;
|
|
wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlen;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlock;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awprot;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awqos;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awready;
|
|
wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awregion;
|
|
wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awsize;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awvalid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bready;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bresp;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bvalid;
|
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rdata;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rid;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rlast;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rready;
|
|
wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rresp;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rvalid;
|
|
wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wdata;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wlast;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wready;
|
|
wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wstrb;
|
|
wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wvalid;
|
|
|
|
x4xx_dram #(
|
|
.ENABLE_DRAM (ENABLE_DRAM),
|
|
.AXI_DWIDTH (DRAM_AXI_DWIDTH),
|
|
.NUM_BANKS (DRAM_NUM_BANKS),
|
|
.PORTS_PER_BANK (DRAM_PORTS_PER_BANK)
|
|
) x4xx_dram_i (
|
|
.sys_rst (sys_rst),
|
|
.dram0_sys_clk_p (dram0_sys_clk_p),
|
|
.dram0_sys_clk_n (dram0_sys_clk_n),
|
|
.dram1_sys_clk_p (dram1_sys_clk_p),
|
|
.dram1_sys_clk_n (dram1_sys_clk_n),
|
|
.dram0_ui_clk (dram0_ui_clk),
|
|
.dram0_ui_clk_sync_rst (dram0_ui_clk_sync_rst),
|
|
.dram1_ui_clk (),
|
|
.dram1_ui_clk_sync_rst (),
|
|
.dram0_ck_t (dram0_ck_t),
|
|
.dram0_ck_c (dram0_ck_c),
|
|
.dram0_cs_n (dram0_cs_n),
|
|
.dram0_act_n (dram0_act_n),
|
|
.dram0_adr (dram0_adr),
|
|
.dram0_ba (dram0_ba),
|
|
.dram0_bg (dram0_bg),
|
|
.dram0_cke (dram0_cke),
|
|
.dram0_odt (dram0_odt),
|
|
.dram0_reset_n (dram0_reset_n),
|
|
.dram0_dm_dbi_n (dram0_dm_dbi_n),
|
|
.dram0_dq (dram0_dq),
|
|
.dram0_dqs_t (dram0_dqs_t),
|
|
.dram0_dqs_c (dram0_dqs_c),
|
|
.dram1_ck_t (dram1_ck_t),
|
|
.dram1_ck_c (dram1_ck_c),
|
|
.dram1_cs_n (dram1_cs_n),
|
|
.dram1_act_n (dram1_act_n),
|
|
.dram1_adr (dram1_adr),
|
|
.dram1_ba (dram1_ba),
|
|
.dram1_bg (dram1_bg),
|
|
.dram1_cke (dram1_cke),
|
|
.dram1_odt (dram1_odt),
|
|
.dram1_reset_n (dram1_reset_n),
|
|
.dram1_dm_dbi_n (dram1_dm_dbi_n),
|
|
.dram1_dq (dram1_dq),
|
|
.dram1_dqs_t (dram1_dqs_t),
|
|
.dram1_dqs_c (dram1_dqs_c),
|
|
.dram_clk (dram_clk),
|
|
.dram_rst (dram_rst),
|
|
.dram_init_calib_complete (),
|
|
.dram0_axi_araddr (dram0_axi_araddr),
|
|
.dram0_axi_arburst (dram0_axi_arburst),
|
|
.dram0_axi_arcache (dram0_axi_arcache),
|
|
.dram0_axi_arid (dram0_axi_arid),
|
|
.dram0_axi_arlen (dram0_axi_arlen),
|
|
.dram0_axi_arlock (dram0_axi_arlock),
|
|
.dram0_axi_arprot (dram0_axi_arprot),
|
|
.dram0_axi_arqos (dram0_axi_arqos),
|
|
.dram0_axi_arready (dram0_axi_arready),
|
|
.dram0_axi_arregion (dram0_axi_arregion),
|
|
.dram0_axi_arsize (dram0_axi_arsize),
|
|
.dram0_axi_arvalid (dram0_axi_arvalid),
|
|
.dram0_axi_awaddr (dram0_axi_awaddr),
|
|
.dram0_axi_awburst (dram0_axi_awburst),
|
|
.dram0_axi_awcache (dram0_axi_awcache),
|
|
.dram0_axi_awid (dram0_axi_awid),
|
|
.dram0_axi_awlen (dram0_axi_awlen),
|
|
.dram0_axi_awlock (dram0_axi_awlock),
|
|
.dram0_axi_awprot (dram0_axi_awprot),
|
|
.dram0_axi_awqos (dram0_axi_awqos),
|
|
.dram0_axi_awready (dram0_axi_awready),
|
|
.dram0_axi_awregion (dram0_axi_awregion),
|
|
.dram0_axi_awsize (dram0_axi_awsize),
|
|
.dram0_axi_awvalid (dram0_axi_awvalid),
|
|
.dram0_axi_bid (dram0_axi_bid),
|
|
.dram0_axi_bready (dram0_axi_bready),
|
|
.dram0_axi_bresp (dram0_axi_bresp),
|
|
.dram0_axi_bvalid (dram0_axi_bvalid),
|
|
.dram0_axi_rdata (dram0_axi_rdata),
|
|
.dram0_axi_rid (dram0_axi_rid),
|
|
.dram0_axi_rlast (dram0_axi_rlast),
|
|
.dram0_axi_rready (dram0_axi_rready),
|
|
.dram0_axi_rresp (dram0_axi_rresp),
|
|
.dram0_axi_rvalid (dram0_axi_rvalid),
|
|
.dram0_axi_wdata (dram0_axi_wdata),
|
|
.dram0_axi_wlast (dram0_axi_wlast),
|
|
.dram0_axi_wready (dram0_axi_wready),
|
|
.dram0_axi_wstrb (dram0_axi_wstrb),
|
|
.dram0_axi_wvalid (dram0_axi_wvalid),
|
|
.dram1_axi_araddr (dram1_axi_araddr),
|
|
.dram1_axi_arburst (dram1_axi_arburst),
|
|
.dram1_axi_arcache (dram1_axi_arcache),
|
|
.dram1_axi_arid (dram1_axi_arid),
|
|
.dram1_axi_arlen (dram1_axi_arlen),
|
|
.dram1_axi_arlock (dram1_axi_arlock),
|
|
.dram1_axi_arprot (dram1_axi_arprot),
|
|
.dram1_axi_arqos (dram1_axi_arqos),
|
|
.dram1_axi_arready (dram1_axi_arready),
|
|
.dram1_axi_arregion (dram1_axi_arregion),
|
|
.dram1_axi_arsize (dram1_axi_arsize),
|
|
.dram1_axi_arvalid (dram1_axi_arvalid),
|
|
.dram1_axi_awaddr (dram1_axi_awaddr),
|
|
.dram1_axi_awburst (dram1_axi_awburst),
|
|
.dram1_axi_awcache (dram1_axi_awcache),
|
|
.dram1_axi_awid (dram1_axi_awid),
|
|
.dram1_axi_awlen (dram1_axi_awlen),
|
|
.dram1_axi_awlock (dram1_axi_awlock),
|
|
.dram1_axi_awprot (dram1_axi_awprot),
|
|
.dram1_axi_awqos (dram1_axi_awqos),
|
|
.dram1_axi_awready (dram1_axi_awready),
|
|
.dram1_axi_awregion (dram1_axi_awregion),
|
|
.dram1_axi_awsize (dram1_axi_awsize),
|
|
.dram1_axi_awvalid (dram1_axi_awvalid),
|
|
.dram1_axi_bid (dram1_axi_bid),
|
|
.dram1_axi_bready (dram1_axi_bready),
|
|
.dram1_axi_bresp (dram1_axi_bresp),
|
|
.dram1_axi_bvalid (dram1_axi_bvalid),
|
|
.dram1_axi_rdata (dram1_axi_rdata),
|
|
.dram1_axi_rid (dram1_axi_rid),
|
|
.dram1_axi_rlast (dram1_axi_rlast),
|
|
.dram1_axi_rready (dram1_axi_rready),
|
|
.dram1_axi_rresp (dram1_axi_rresp),
|
|
.dram1_axi_rvalid (dram1_axi_rvalid),
|
|
.dram1_axi_wdata (dram1_axi_wdata),
|
|
.dram1_axi_wlast (dram1_axi_wlast),
|
|
.dram1_axi_wready (dram1_axi_wready),
|
|
.dram1_axi_wstrb (dram1_axi_wstrb),
|
|
.dram1_axi_wvalid (dram1_axi_wvalid)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// RFNoC Image Core
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Calculate how many bits wide each channel is
|
|
localparam CHAN_W = 32 * RADIO_SPC;
|
|
wire [NUM_CH_PER_DB-1:0] rx_stb0, rx_stb1;
|
|
wire [NUM_CH_PER_DB-1:0] tx_stb0, tx_stb1;
|
|
wire [NUM_CH_PER_DB-1:0] rx_running0, rx_running1;
|
|
wire [NUM_CH_PER_DB-1:0] tx_running0, tx_running1;
|
|
wire [CHAN_W*NUM_CH_PER_DB-1:0] rx_data0, rx_data1;
|
|
wire [CHAN_W*NUM_CH_PER_DB-1:0] tx_data0, tx_data1;
|
|
|
|
// Separate out signals to the radio blocks, 1 per dboard, 2 assumed dboards
|
|
// [signal name]0 is lower half of a signal, and [signal name]1 is top half
|
|
// ex: rx_stb is 1 bit per channel with a width of NUM_CHANNELS
|
|
// rx_stb0 is lower half, NUM_CH_PER_DB-1:0
|
|
// rx_stb1 is top half, starting at NUM_CH_PER_DB
|
|
// Datapaths follow the same pattern but with CHAN_W factored in
|
|
// output paths can just concatenate top/bottom half signals
|
|
assign rx_stb0 = rx_stb[NUM_CH_PER_DB*0+:NUM_CH_PER_DB];
|
|
assign rx_stb1 = rx_stb[NUM_CH_PER_DB*1+:NUM_CH_PER_DB];
|
|
assign rx_running = { rx_running1, rx_running0};
|
|
assign rx_data0 = rx_data[CHAN_W*NUM_CH_PER_DB*0+:CHAN_W*NUM_CH_PER_DB];
|
|
assign rx_data1 = rx_data[CHAN_W*NUM_CH_PER_DB*1+:CHAN_W*NUM_CH_PER_DB];
|
|
assign tx_stb0 = tx_stb[NUM_CH_PER_DB*0+:NUM_CH_PER_DB];
|
|
assign tx_stb1 = tx_stb[NUM_CH_PER_DB*1+:NUM_CH_PER_DB];
|
|
assign tx_running = { tx_running1, tx_running0};
|
|
assign tx_data = { tx_data1, tx_data0};
|
|
|
|
localparam PORT_W = 512; // Set to max value; unused bits will be ignored.
|
|
localparam ENET0_W = ENET_WIDTHS[32*0 +: 32];
|
|
localparam ENET1_W = ENET_WIDTHS[32*1 +: 32];
|
|
localparam ENET2_W = ENET_WIDTHS[32*2 +: 32];
|
|
localparam ENET3_W = ENET_WIDTHS[32*3 +: 32];
|
|
localparam ENET4_W = ENET_WIDTHS[32*4 +: 32];
|
|
|
|
rfnoc_image_core #(
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.CHDR_W (CHDR_W),
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.PORT_W (PORT_W),
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.ETH0_W (ENET0_W),
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.ETH1_W (ENET1_W),
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.ETH2_W (ENET2_W),
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.ETH3_W (ENET3_W),
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.ETH4_W (ENET4_W),
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.DMA_W (DMA_W),
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.MTU (MTU),
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.PROTOVER (RFNOC_PROTOVER),
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.RADIO_NIPC (RADIO_SPC)
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) rfnoc_image_core_i (
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.chdr_aclk (rfnoc_chdr_clk),
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.ctrl_aclk (rfnoc_ctrl_clk),
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.core_arst (rfnoc_ctrl_rst),
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`ifdef X440
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.radio0_clk (radio_clk[0]),
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.radio0_2x_clk (radio_clk_2x[0]),
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.radio1_clk (radio_clk[1]),
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.radio1_2x_clk (radio_clk_2x[1]),
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`else
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.radio_clk (radio_clk[0]),
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.radio_2x_clk (radio_clk_2x[0]),
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`endif
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.dram_clk (dram_clk),
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.ce_clk (ce_clk),
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.device_id (device_id),
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.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),
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.m_ctrlport_radio0_req_rd (ctrlport_radio_req_rd [0* 1+: 1]),
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.m_ctrlport_radio0_req_addr (ctrlport_radio_req_addr [0*20+:20]),
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.m_ctrlport_radio0_req_data (ctrlport_radio_req_data [0*32+:32]),
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.m_ctrlport_radio0_req_byte_en (ctrlport_radio_req_byte_en [0* 4+: 4]),
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.m_ctrlport_radio0_req_has_time (ctrlport_radio_req_has_time[0* 1+: 1]),
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.m_ctrlport_radio0_req_time (ctrlport_radio_req_time [0*64+:64]),
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.m_ctrlport_radio0_resp_ack (ctrlport_radio_resp_ack [0* 1+: 1]),
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.m_ctrlport_radio0_resp_status (ctrlport_radio_resp_status [0* 2+: 2]),
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.m_ctrlport_radio0_resp_data (ctrlport_radio_resp_data [0*32+:32]),
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.m_ctrlport_radio1_req_wr (ctrlport_radio_req_wr [1* 1+: 1]),
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.m_ctrlport_radio1_req_rd (ctrlport_radio_req_rd [1* 1+: 1]),
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.m_ctrlport_radio1_req_addr (ctrlport_radio_req_addr [1*20+:20]),
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.m_ctrlport_radio1_req_data (ctrlport_radio_req_data [1*32+:32]),
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.m_ctrlport_radio1_req_byte_en (ctrlport_radio_req_byte_en [1* 4+: 4]),
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.m_ctrlport_radio1_req_has_time (ctrlport_radio_req_has_time[1* 1+: 1]),
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.m_ctrlport_radio1_req_time (ctrlport_radio_req_time [1*64+:64]),
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.m_ctrlport_radio1_resp_ack (ctrlport_radio_resp_ack [1* 1+: 1]),
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.m_ctrlport_radio1_resp_status (ctrlport_radio_resp_status [1* 2+: 2]),
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.m_ctrlport_radio1_resp_data (ctrlport_radio_resp_data [1*32+:32]),
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.radio_rx_stb_radio1 ({ rx_stb1}),
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.radio_rx_data_radio1 ({ rx_data1}),
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.radio_rx_running_radio1 ({ rx_running1}),
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.radio_tx_stb_radio1 ({ tx_stb1}),
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.radio_tx_data_radio1 ({ tx_data1}),
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.radio_tx_running_radio1 ({ tx_running1}),
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.radio_rx_stb_radio0 ({ rx_stb0}),
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.radio_rx_data_radio0 ({ rx_data0}),
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.radio_rx_running_radio0 ({ rx_running0}),
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.radio_tx_stb_radio0 ({ tx_stb0}),
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.radio_tx_data_radio0 ({ tx_data0}),
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.radio_tx_running_radio0 ({ tx_running0}),
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`ifdef X440
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.radio_time0 (radio_time[0*64+:64]),
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.radio_time1 (radio_time[1*64+:64]),
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`else
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.radio_time (radio_time[0*64+:64]),
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`endif
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.dram0_axi_rst (dram_rst),
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.dram0_m_axi_awid (dram0_axi_awid),
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.dram0_m_axi_awaddr (dram0_axi_awaddr),
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.dram0_m_axi_awlen (dram0_axi_awlen),
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.dram0_m_axi_awsize (dram0_axi_awsize),
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.dram0_m_axi_awburst (dram0_axi_awburst),
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|
.dram0_m_axi_awlock (dram0_axi_awlock),
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.dram0_m_axi_awcache (dram0_axi_awcache),
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.dram0_m_axi_awprot (dram0_axi_awprot),
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.dram0_m_axi_awqos (dram0_axi_awqos),
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.dram0_m_axi_awregion (dram0_axi_awregion),
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.dram0_m_axi_awuser (),
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|
.dram0_m_axi_awvalid (dram0_axi_awvalid),
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|
.dram0_m_axi_awready (dram0_axi_awready),
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|
.dram0_m_axi_wdata (dram0_axi_wdata),
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|
.dram0_m_axi_wstrb (dram0_axi_wstrb),
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|
.dram0_m_axi_wlast (dram0_axi_wlast),
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|
.dram0_m_axi_wuser (),
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|
.dram0_m_axi_wvalid (dram0_axi_wvalid),
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|
.dram0_m_axi_wready (dram0_axi_wready),
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|
.dram0_m_axi_bid (dram0_axi_bid),
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|
.dram0_m_axi_bresp (dram0_axi_bresp),
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|
.dram0_m_axi_buser (0),
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|
.dram0_m_axi_bvalid (dram0_axi_bvalid),
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|
.dram0_m_axi_bready (dram0_axi_bready),
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|
.dram0_m_axi_arid (dram0_axi_arid),
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|
.dram0_m_axi_araddr (dram0_axi_araddr),
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|
.dram0_m_axi_arlen (dram0_axi_arlen),
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.dram0_m_axi_arsize (dram0_axi_arsize),
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.dram0_m_axi_arburst (dram0_axi_arburst),
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|
.dram0_m_axi_arlock (dram0_axi_arlock),
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|
.dram0_m_axi_arcache (dram0_axi_arcache),
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.dram0_m_axi_arprot (dram0_axi_arprot),
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|
.dram0_m_axi_arqos (dram0_axi_arqos),
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|
.dram0_m_axi_arregion (dram0_axi_arregion),
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|
.dram0_m_axi_aruser (),
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|
.dram0_m_axi_arvalid (dram0_axi_arvalid),
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|
.dram0_m_axi_arready (dram0_axi_arready),
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|
.dram0_m_axi_rid (dram0_axi_rid),
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|
.dram0_m_axi_rdata (dram0_axi_rdata),
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|
.dram0_m_axi_rresp (dram0_axi_rresp),
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|
.dram0_m_axi_rlast (dram0_axi_rlast),
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|
.dram0_m_axi_ruser (0),
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|
.dram0_m_axi_rvalid (dram0_axi_rvalid),
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|
.dram0_m_axi_rready (dram0_axi_rready),
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|
.dram1_axi_rst (dram_rst),
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|
.dram1_m_axi_awid (dram1_axi_awid),
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|
.dram1_m_axi_awaddr (dram1_axi_awaddr),
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|
.dram1_m_axi_awlen (dram1_axi_awlen),
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|
.dram1_m_axi_awsize (dram1_axi_awsize),
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|
.dram1_m_axi_awburst (dram1_axi_awburst),
|
|
.dram1_m_axi_awlock (dram1_axi_awlock),
|
|
.dram1_m_axi_awcache (dram1_axi_awcache),
|
|
.dram1_m_axi_awprot (dram1_axi_awprot),
|
|
.dram1_m_axi_awqos (dram1_axi_awqos),
|
|
.dram1_m_axi_awregion (dram1_axi_awregion),
|
|
.dram1_m_axi_awuser (),
|
|
.dram1_m_axi_awvalid (dram1_axi_awvalid),
|
|
.dram1_m_axi_awready (dram1_axi_awready),
|
|
.dram1_m_axi_wdata (dram1_axi_wdata),
|
|
.dram1_m_axi_wstrb (dram1_axi_wstrb),
|
|
.dram1_m_axi_wlast (dram1_axi_wlast),
|
|
.dram1_m_axi_wuser (),
|
|
.dram1_m_axi_wvalid (dram1_axi_wvalid),
|
|
.dram1_m_axi_wready (dram1_axi_wready),
|
|
.dram1_m_axi_bid (dram1_axi_bid),
|
|
.dram1_m_axi_bresp (dram1_axi_bresp),
|
|
.dram1_m_axi_buser (0),
|
|
.dram1_m_axi_bvalid (dram1_axi_bvalid),
|
|
.dram1_m_axi_bready (dram1_axi_bready),
|
|
.dram1_m_axi_arid (dram1_axi_arid),
|
|
.dram1_m_axi_araddr (dram1_axi_araddr),
|
|
.dram1_m_axi_arlen (dram1_axi_arlen),
|
|
.dram1_m_axi_arsize (dram1_axi_arsize),
|
|
.dram1_m_axi_arburst (dram1_axi_arburst),
|
|
.dram1_m_axi_arlock (dram1_axi_arlock),
|
|
.dram1_m_axi_arcache (dram1_axi_arcache),
|
|
.dram1_m_axi_arprot (dram1_axi_arprot),
|
|
.dram1_m_axi_arqos (dram1_axi_arqos),
|
|
.dram1_m_axi_arregion (dram1_axi_arregion),
|
|
.dram1_m_axi_aruser (),
|
|
.dram1_m_axi_arvalid (dram1_axi_arvalid),
|
|
.dram1_m_axi_arready (dram1_axi_arready),
|
|
.dram1_m_axi_rid (dram1_axi_rid),
|
|
.dram1_m_axi_rdata (dram1_axi_rdata),
|
|
.dram1_m_axi_rresp (dram1_axi_rresp),
|
|
.dram1_m_axi_rlast (dram1_axi_rlast),
|
|
.dram1_m_axi_ruser (0),
|
|
.dram1_m_axi_rvalid (dram1_axi_rvalid),
|
|
.dram1_m_axi_rready (dram1_axi_rready),
|
|
.s_eth0_tdata (e2v_tdata [0*ENET_W +: ENET0_W]),
|
|
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
|
|
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
|
|
.s_eth0_tready (e2v_tready [0* 1 +: 1]),
|
|
.m_eth0_tdata (v2e_tdata [0*ENET_W +: ENET0_W]),
|
|
.m_eth0_tlast (v2e_tlast [0* 1 +: 1]),
|
|
.m_eth0_tvalid (v2e_tvalid [0* 1 +: 1]),
|
|
.m_eth0_tready (v2e_tready [0* 1 +: 1]),
|
|
.s_eth1_tdata (e2v_tdata [1*ENET_W +: ENET1_W]),
|
|
.s_eth1_tlast (e2v_tlast [1* 1 +: 1]),
|
|
.s_eth1_tvalid (e2v_tvalid [1* 1 +: 1]),
|
|
.s_eth1_tready (e2v_tready [1* 1 +: 1]),
|
|
.m_eth1_tdata (v2e_tdata [1*ENET_W +: ENET1_W]),
|
|
.m_eth1_tlast (v2e_tlast [1* 1 +: 1]),
|
|
.m_eth1_tvalid (v2e_tvalid [1* 1 +: 1]),
|
|
.m_eth1_tready (v2e_tready [1* 1 +: 1]),
|
|
.s_eth2_tdata (e2v_tdata [2*ENET_W +: ENET2_W]),
|
|
.s_eth2_tlast (e2v_tlast [2* 1 +: 1]),
|
|
.s_eth2_tvalid (e2v_tvalid [2* 1 +: 1]),
|
|
.s_eth2_tready (e2v_tready [2* 1 +: 1]),
|
|
.m_eth2_tdata (v2e_tdata [2*ENET_W +: ENET2_W]),
|
|
.m_eth2_tlast (v2e_tlast [2* 1 +: 1]),
|
|
.m_eth2_tvalid (v2e_tvalid [2* 1 +: 1]),
|
|
.m_eth2_tready (v2e_tready [2* 1 +: 1]),
|
|
.s_eth3_tdata (e2v_tdata [3*ENET_W +: ENET3_W]),
|
|
.s_eth3_tlast (e2v_tlast [3* 1 +: 1]),
|
|
.s_eth3_tvalid (e2v_tvalid [3* 1 +: 1]),
|
|
.s_eth3_tready (e2v_tready [3* 1 +: 1]),
|
|
.m_eth3_tdata (v2e_tdata [3*ENET_W +: ENET3_W]),
|
|
.m_eth3_tlast (v2e_tlast [3* 1 +: 1]),
|
|
.m_eth3_tvalid (v2e_tvalid [3* 1 +: 1]),
|
|
.m_eth3_tready (v2e_tready [3* 1 +: 1]),
|
|
.s_eth4_tdata (e2v_tdata [4*ENET_W +: ENET4_W]),
|
|
.s_eth4_tlast (e2v_tlast [4* 1 +: 1]),
|
|
.s_eth4_tvalid (e2v_tvalid [4* 1 +: 1]),
|
|
.s_eth4_tready (e2v_tready [4* 1 +: 1]),
|
|
.m_eth4_tdata (v2e_tdata [4*ENET_W +: ENET4_W]),
|
|
.m_eth4_tlast (v2e_tlast [4* 1 +: 1]),
|
|
.m_eth4_tvalid (v2e_tvalid [4* 1 +: 1]),
|
|
.m_eth4_tready (v2e_tready [4* 1 +: 1]),
|
|
.s_dma_tdata (dmai_tdata),
|
|
.s_dma_tlast (dmai_tlast),
|
|
.s_dma_tvalid (dmai_tvalid),
|
|
.s_dma_tready (dmai_tready),
|
|
.m_dma_tdata (dmao_tdata),
|
|
.m_dma_tlast (dmao_tlast),
|
|
.m_dma_tvalid (dmao_tvalid),
|
|
.m_dma_tready (dmao_tready)
|
|
);
|
|
|
|
endmodule
|