fpga: x400: Split DRAM interface into two banks
This updates the RFNoC image cores to separate the two DRAM banks on X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM banks shared the same DRAM port, named "dram", which created some confusion. The Replay block has also been duplicated in the bitstreams that use both banks, so we now have one Replay block per bank. Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
This commit is contained in:
Wade Fife
+255
-129
@@ -421,9 +421,10 @@ module x4xx_core #(
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`define DRAM_W 64
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`endif
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localparam DRAM_AXI_DWIDTH = `DRAM_W;
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localparam ENABLE_DRAM = (`DRAM_CH > 0);
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localparam DRAM_NUM_PORTS = `DRAM_CH;
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localparam ENABLE_DRAM = (`DRAM_CH > 0 && `DRAM_BANKS > 0);
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localparam DRAM_AXI_DWIDTH = `DRAM_W;
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localparam DRAM_NUM_BANKS = ENABLE_DRAM ? `DRAM_BANKS : 1;
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localparam DRAM_PORTS_PER_BANK = ENABLE_DRAM ? `DRAM_CH / DRAM_NUM_BANKS : 1;
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wire dram0_ui_clk;
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wire dram0_ui_clk_sync_rst;
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@@ -432,50 +433,91 @@ module x4xx_core #(
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wire dram_rst = dram0_ui_clk_sync_rst;
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wire sys_rst = rfnoc_chdr_rst;
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wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_araddr;
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wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_arburst;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arcache;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arid;
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wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_arlen;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arlock;
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wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arprot;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arqos;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arready;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_arregion;
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wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_arsize;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_arvalid;
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wire [ 32*DRAM_NUM_PORTS-1:0] dram_axi_awaddr;
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wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_awburst;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awcache;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awid;
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wire [ 8*DRAM_NUM_PORTS-1:0] dram_axi_awlen;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awlock;
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wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awprot;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awqos;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awready;
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wire [ 4*DRAM_NUM_PORTS-1:0] dram_axi_awregion;
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wire [ 3*DRAM_NUM_PORTS-1:0] dram_axi_awsize;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_awvalid;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bid;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bready;
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wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_bresp;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_bvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_rdata;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rid;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rlast;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rready;
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wire [ 2*DRAM_NUM_PORTS-1:0] dram_axi_rresp;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_rvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_NUM_PORTS-1:0] dram_axi_wdata;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wlast;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wready;
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wire [DRAM_AXI_DWIDTH/8*DRAM_NUM_PORTS-1:0] dram_axi_wstrb;
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wire [ 1*DRAM_NUM_PORTS-1:0] dram_axi_wvalid;
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wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_araddr;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arburst;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arcache;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arid;
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wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlen;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arlock;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arprot;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arqos;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arready;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arregion;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arsize;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_arvalid;
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wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awaddr;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awburst;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awcache;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awid;
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wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlen;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awlock;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awprot;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awqos;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awready;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awregion;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awsize;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_awvalid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bready;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bresp;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_bvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rdata;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rlast;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rready;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rresp;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_rvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wdata;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wlast;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wready;
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wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wstrb;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram0_axi_wvalid;
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wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_araddr;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arburst;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arcache;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arid;
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wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlen;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arlock;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arprot;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arqos;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arready;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arregion;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arsize;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_arvalid;
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wire [ 32*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awaddr;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awburst;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awcache;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awid;
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wire [ 8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlen;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awlock;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awprot;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awqos;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awready;
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wire [ 4*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awregion;
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wire [ 3*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awsize;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_awvalid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bready;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bresp;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_bvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rdata;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rid;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rlast;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rready;
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wire [ 2*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rresp;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_rvalid;
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wire [ DRAM_AXI_DWIDTH*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wdata;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wlast;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wready;
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wire [DRAM_AXI_DWIDTH/8*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wstrb;
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wire [ 1*DRAM_PORTS_PER_BANK-1:0] dram1_axi_wvalid;
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x4xx_dram #(
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.ENABLE_DRAM (ENABLE_DRAM),
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.AXI_DWIDTH (DRAM_AXI_DWIDTH),
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.NUM_PORTS (DRAM_NUM_PORTS)
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.ENABLE_DRAM (ENABLE_DRAM),
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.AXI_DWIDTH (DRAM_AXI_DWIDTH),
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.NUM_BANKS (DRAM_NUM_BANKS),
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.PORTS_PER_BANK (DRAM_PORTS_PER_BANK)
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) x4xx_dram_i (
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.sys_rst (sys_rst),
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.dram0_sys_clk_p (dram0_sys_clk_p),
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@@ -517,45 +559,84 @@ module x4xx_core #(
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.dram_clk (dram_clk),
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.dram_rst (dram_rst),
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.dram_init_calib_complete (),
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.dram_axi_araddr (dram_axi_araddr),
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.dram_axi_arburst (dram_axi_arburst),
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.dram_axi_arcache (dram_axi_arcache),
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.dram_axi_arid (dram_axi_arid),
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.dram_axi_arlen (dram_axi_arlen),
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.dram_axi_arlock (dram_axi_arlock),
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.dram_axi_arprot (dram_axi_arprot),
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.dram_axi_arqos (dram_axi_arqos),
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.dram_axi_arready (dram_axi_arready),
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.dram_axi_arregion (dram_axi_arregion),
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.dram_axi_arsize (dram_axi_arsize),
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.dram_axi_arvalid (dram_axi_arvalid),
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.dram_axi_awaddr (dram_axi_awaddr),
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.dram_axi_awburst (dram_axi_awburst),
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.dram_axi_awcache (dram_axi_awcache),
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.dram_axi_awid (dram_axi_awid),
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.dram_axi_awlen (dram_axi_awlen),
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.dram_axi_awlock (dram_axi_awlock),
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.dram_axi_awprot (dram_axi_awprot),
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.dram_axi_awqos (dram_axi_awqos),
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.dram_axi_awready (dram_axi_awready),
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.dram_axi_awregion (dram_axi_awregion),
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.dram_axi_awsize (dram_axi_awsize),
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.dram_axi_awvalid (dram_axi_awvalid),
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.dram_axi_bid (dram_axi_bid),
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.dram_axi_bready (dram_axi_bready),
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.dram_axi_bresp (dram_axi_bresp),
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.dram_axi_bvalid (dram_axi_bvalid),
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.dram_axi_rdata (dram_axi_rdata),
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.dram_axi_rid (dram_axi_rid),
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.dram_axi_rlast (dram_axi_rlast),
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.dram_axi_rready (dram_axi_rready),
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.dram_axi_rresp (dram_axi_rresp),
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.dram_axi_rvalid (dram_axi_rvalid),
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.dram_axi_wdata (dram_axi_wdata),
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.dram_axi_wlast (dram_axi_wlast),
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.dram_axi_wready (dram_axi_wready),
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.dram_axi_wstrb (dram_axi_wstrb),
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.dram_axi_wvalid (dram_axi_wvalid)
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.dram0_axi_araddr (dram0_axi_araddr),
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.dram0_axi_arburst (dram0_axi_arburst),
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.dram0_axi_arcache (dram0_axi_arcache),
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.dram0_axi_arid (dram0_axi_arid),
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.dram0_axi_arlen (dram0_axi_arlen),
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.dram0_axi_arlock (dram0_axi_arlock),
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.dram0_axi_arprot (dram0_axi_arprot),
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.dram0_axi_arqos (dram0_axi_arqos),
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.dram0_axi_arready (dram0_axi_arready),
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.dram0_axi_arregion (dram0_axi_arregion),
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.dram0_axi_arsize (dram0_axi_arsize),
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.dram0_axi_arvalid (dram0_axi_arvalid),
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.dram0_axi_awaddr (dram0_axi_awaddr),
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.dram0_axi_awburst (dram0_axi_awburst),
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.dram0_axi_awcache (dram0_axi_awcache),
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.dram0_axi_awid (dram0_axi_awid),
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.dram0_axi_awlen (dram0_axi_awlen),
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.dram0_axi_awlock (dram0_axi_awlock),
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.dram0_axi_awprot (dram0_axi_awprot),
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.dram0_axi_awqos (dram0_axi_awqos),
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.dram0_axi_awready (dram0_axi_awready),
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.dram0_axi_awregion (dram0_axi_awregion),
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.dram0_axi_awsize (dram0_axi_awsize),
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.dram0_axi_awvalid (dram0_axi_awvalid),
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.dram0_axi_bid (dram0_axi_bid),
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.dram0_axi_bready (dram0_axi_bready),
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.dram0_axi_bresp (dram0_axi_bresp),
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.dram0_axi_bvalid (dram0_axi_bvalid),
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.dram0_axi_rdata (dram0_axi_rdata),
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.dram0_axi_rid (dram0_axi_rid),
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.dram0_axi_rlast (dram0_axi_rlast),
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.dram0_axi_rready (dram0_axi_rready),
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.dram0_axi_rresp (dram0_axi_rresp),
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.dram0_axi_rvalid (dram0_axi_rvalid),
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.dram0_axi_wdata (dram0_axi_wdata),
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.dram0_axi_wlast (dram0_axi_wlast),
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.dram0_axi_wready (dram0_axi_wready),
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.dram0_axi_wstrb (dram0_axi_wstrb),
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.dram0_axi_wvalid (dram0_axi_wvalid),
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.dram1_axi_araddr (dram1_axi_araddr),
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.dram1_axi_arburst (dram1_axi_arburst),
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.dram1_axi_arcache (dram1_axi_arcache),
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.dram1_axi_arid (dram1_axi_arid),
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.dram1_axi_arlen (dram1_axi_arlen),
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.dram1_axi_arlock (dram1_axi_arlock),
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.dram1_axi_arprot (dram1_axi_arprot),
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.dram1_axi_arqos (dram1_axi_arqos),
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.dram1_axi_arready (dram1_axi_arready),
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.dram1_axi_arregion (dram1_axi_arregion),
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.dram1_axi_arsize (dram1_axi_arsize),
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.dram1_axi_arvalid (dram1_axi_arvalid),
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.dram1_axi_awaddr (dram1_axi_awaddr),
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.dram1_axi_awburst (dram1_axi_awburst),
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.dram1_axi_awcache (dram1_axi_awcache),
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.dram1_axi_awid (dram1_axi_awid),
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.dram1_axi_awlen (dram1_axi_awlen),
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.dram1_axi_awlock (dram1_axi_awlock),
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.dram1_axi_awprot (dram1_axi_awprot),
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.dram1_axi_awqos (dram1_axi_awqos),
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.dram1_axi_awready (dram1_axi_awready),
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.dram1_axi_awregion (dram1_axi_awregion),
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.dram1_axi_awsize (dram1_axi_awsize),
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.dram1_axi_awvalid (dram1_axi_awvalid),
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.dram1_axi_bid (dram1_axi_bid),
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.dram1_axi_bready (dram1_axi_bready),
|
||||
.dram1_axi_bresp (dram1_axi_bresp),
|
||||
.dram1_axi_bvalid (dram1_axi_bvalid),
|
||||
.dram1_axi_rdata (dram1_axi_rdata),
|
||||
.dram1_axi_rid (dram1_axi_rid),
|
||||
.dram1_axi_rlast (dram1_axi_rlast),
|
||||
.dram1_axi_rready (dram1_axi_rready),
|
||||
.dram1_axi_rresp (dram1_axi_rresp),
|
||||
.dram1_axi_rvalid (dram1_axi_rvalid),
|
||||
.dram1_axi_wdata (dram1_axi_wdata),
|
||||
.dram1_axi_wlast (dram1_axi_wlast),
|
||||
.dram1_axi_wready (dram1_axi_wready),
|
||||
.dram1_axi_wstrb (dram1_axi_wstrb),
|
||||
.dram1_axi_wvalid (dram1_axi_wvalid)
|
||||
);
|
||||
|
||||
|
||||
@@ -662,51 +743,96 @@ module x4xx_core #(
|
||||
`else
|
||||
.radio_time (radio_time[0*64+:64]),
|
||||
`endif
|
||||
.axi_rst (dram_rst),
|
||||
.m_axi_awid (dram_axi_awid),
|
||||
.m_axi_awaddr (dram_axi_awaddr),
|
||||
.m_axi_awlen (dram_axi_awlen),
|
||||
.m_axi_awsize (dram_axi_awsize),
|
||||
.m_axi_awburst (dram_axi_awburst),
|
||||
.m_axi_awlock (dram_axi_awlock),
|
||||
.m_axi_awcache (dram_axi_awcache),
|
||||
.m_axi_awprot (dram_axi_awprot),
|
||||
.m_axi_awqos (dram_axi_awqos),
|
||||
.m_axi_awregion (dram_axi_awregion),
|
||||
.m_axi_awuser (),
|
||||
.m_axi_awvalid (dram_axi_awvalid),
|
||||
.m_axi_awready (dram_axi_awready),
|
||||
.m_axi_wdata (dram_axi_wdata),
|
||||
.m_axi_wstrb (dram_axi_wstrb),
|
||||
.m_axi_wlast (dram_axi_wlast),
|
||||
.m_axi_wuser (),
|
||||
.m_axi_wvalid (dram_axi_wvalid),
|
||||
.m_axi_wready (dram_axi_wready),
|
||||
.m_axi_bid (dram_axi_bid),
|
||||
.m_axi_bresp (dram_axi_bresp),
|
||||
.m_axi_buser (0),
|
||||
.m_axi_bvalid (dram_axi_bvalid),
|
||||
.m_axi_bready (dram_axi_bready),
|
||||
.m_axi_arid (dram_axi_arid),
|
||||
.m_axi_araddr (dram_axi_araddr),
|
||||
.m_axi_arlen (dram_axi_arlen),
|
||||
.m_axi_arsize (dram_axi_arsize),
|
||||
.m_axi_arburst (dram_axi_arburst),
|
||||
.m_axi_arlock (dram_axi_arlock),
|
||||
.m_axi_arcache (dram_axi_arcache),
|
||||
.m_axi_arprot (dram_axi_arprot),
|
||||
.m_axi_arqos (dram_axi_arqos),
|
||||
.m_axi_arregion (dram_axi_arregion),
|
||||
.m_axi_aruser (),
|
||||
.m_axi_arvalid (dram_axi_arvalid),
|
||||
.m_axi_arready (dram_axi_arready),
|
||||
.m_axi_rid (dram_axi_rid),
|
||||
.m_axi_rdata (dram_axi_rdata),
|
||||
.m_axi_rresp (dram_axi_rresp),
|
||||
.m_axi_rlast (dram_axi_rlast),
|
||||
.m_axi_ruser (0),
|
||||
.m_axi_rvalid (dram_axi_rvalid),
|
||||
.m_axi_rready (dram_axi_rready),
|
||||
.dram0_axi_rst (dram_rst),
|
||||
.dram0_m_axi_awid (dram0_axi_awid),
|
||||
.dram0_m_axi_awaddr (dram0_axi_awaddr),
|
||||
.dram0_m_axi_awlen (dram0_axi_awlen),
|
||||
.dram0_m_axi_awsize (dram0_axi_awsize),
|
||||
.dram0_m_axi_awburst (dram0_axi_awburst),
|
||||
.dram0_m_axi_awlock (dram0_axi_awlock),
|
||||
.dram0_m_axi_awcache (dram0_axi_awcache),
|
||||
.dram0_m_axi_awprot (dram0_axi_awprot),
|
||||
.dram0_m_axi_awqos (dram0_axi_awqos),
|
||||
.dram0_m_axi_awregion (dram0_axi_awregion),
|
||||
.dram0_m_axi_awuser (),
|
||||
.dram0_m_axi_awvalid (dram0_axi_awvalid),
|
||||
.dram0_m_axi_awready (dram0_axi_awready),
|
||||
.dram0_m_axi_wdata (dram0_axi_wdata),
|
||||
.dram0_m_axi_wstrb (dram0_axi_wstrb),
|
||||
.dram0_m_axi_wlast (dram0_axi_wlast),
|
||||
.dram0_m_axi_wuser (),
|
||||
.dram0_m_axi_wvalid (dram0_axi_wvalid),
|
||||
.dram0_m_axi_wready (dram0_axi_wready),
|
||||
.dram0_m_axi_bid (dram0_axi_bid),
|
||||
.dram0_m_axi_bresp (dram0_axi_bresp),
|
||||
.dram0_m_axi_buser (0),
|
||||
.dram0_m_axi_bvalid (dram0_axi_bvalid),
|
||||
.dram0_m_axi_bready (dram0_axi_bready),
|
||||
.dram0_m_axi_arid (dram0_axi_arid),
|
||||
.dram0_m_axi_araddr (dram0_axi_araddr),
|
||||
.dram0_m_axi_arlen (dram0_axi_arlen),
|
||||
.dram0_m_axi_arsize (dram0_axi_arsize),
|
||||
.dram0_m_axi_arburst (dram0_axi_arburst),
|
||||
.dram0_m_axi_arlock (dram0_axi_arlock),
|
||||
.dram0_m_axi_arcache (dram0_axi_arcache),
|
||||
.dram0_m_axi_arprot (dram0_axi_arprot),
|
||||
.dram0_m_axi_arqos (dram0_axi_arqos),
|
||||
.dram0_m_axi_arregion (dram0_axi_arregion),
|
||||
.dram0_m_axi_aruser (),
|
||||
.dram0_m_axi_arvalid (dram0_axi_arvalid),
|
||||
.dram0_m_axi_arready (dram0_axi_arready),
|
||||
.dram0_m_axi_rid (dram0_axi_rid),
|
||||
.dram0_m_axi_rdata (dram0_axi_rdata),
|
||||
.dram0_m_axi_rresp (dram0_axi_rresp),
|
||||
.dram0_m_axi_rlast (dram0_axi_rlast),
|
||||
.dram0_m_axi_ruser (0),
|
||||
.dram0_m_axi_rvalid (dram0_axi_rvalid),
|
||||
.dram0_m_axi_rready (dram0_axi_rready),
|
||||
.dram1_axi_rst (dram_rst),
|
||||
.dram1_m_axi_awid (dram1_axi_awid),
|
||||
.dram1_m_axi_awaddr (dram1_axi_awaddr),
|
||||
.dram1_m_axi_awlen (dram1_axi_awlen),
|
||||
.dram1_m_axi_awsize (dram1_axi_awsize),
|
||||
.dram1_m_axi_awburst (dram1_axi_awburst),
|
||||
.dram1_m_axi_awlock (dram1_axi_awlock),
|
||||
.dram1_m_axi_awcache (dram1_axi_awcache),
|
||||
.dram1_m_axi_awprot (dram1_axi_awprot),
|
||||
.dram1_m_axi_awqos (dram1_axi_awqos),
|
||||
.dram1_m_axi_awregion (dram1_axi_awregion),
|
||||
.dram1_m_axi_awuser (),
|
||||
.dram1_m_axi_awvalid (dram1_axi_awvalid),
|
||||
.dram1_m_axi_awready (dram1_axi_awready),
|
||||
.dram1_m_axi_wdata (dram1_axi_wdata),
|
||||
.dram1_m_axi_wstrb (dram1_axi_wstrb),
|
||||
.dram1_m_axi_wlast (dram1_axi_wlast),
|
||||
.dram1_m_axi_wuser (),
|
||||
.dram1_m_axi_wvalid (dram1_axi_wvalid),
|
||||
.dram1_m_axi_wready (dram1_axi_wready),
|
||||
.dram1_m_axi_bid (dram1_axi_bid),
|
||||
.dram1_m_axi_bresp (dram1_axi_bresp),
|
||||
.dram1_m_axi_buser (0),
|
||||
.dram1_m_axi_bvalid (dram1_axi_bvalid),
|
||||
.dram1_m_axi_bready (dram1_axi_bready),
|
||||
.dram1_m_axi_arid (dram1_axi_arid),
|
||||
.dram1_m_axi_araddr (dram1_axi_araddr),
|
||||
.dram1_m_axi_arlen (dram1_axi_arlen),
|
||||
.dram1_m_axi_arsize (dram1_axi_arsize),
|
||||
.dram1_m_axi_arburst (dram1_axi_arburst),
|
||||
.dram1_m_axi_arlock (dram1_axi_arlock),
|
||||
.dram1_m_axi_arcache (dram1_axi_arcache),
|
||||
.dram1_m_axi_arprot (dram1_axi_arprot),
|
||||
.dram1_m_axi_arqos (dram1_axi_arqos),
|
||||
.dram1_m_axi_arregion (dram1_axi_arregion),
|
||||
.dram1_m_axi_aruser (),
|
||||
.dram1_m_axi_arvalid (dram1_axi_arvalid),
|
||||
.dram1_m_axi_arready (dram1_axi_arready),
|
||||
.dram1_m_axi_rid (dram1_axi_rid),
|
||||
.dram1_m_axi_rdata (dram1_axi_rdata),
|
||||
.dram1_m_axi_rresp (dram1_axi_rresp),
|
||||
.dram1_m_axi_rlast (dram1_axi_rlast),
|
||||
.dram1_m_axi_ruser (0),
|
||||
.dram1_m_axi_rvalid (dram1_axi_rvalid),
|
||||
.dram1_m_axi_rready (dram1_axi_rready),
|
||||
.s_eth0_tdata (e2v_tdata [0*ENET_W +: ENET0_W]),
|
||||
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
|
||||
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
|
||||
|
||||
Reference in New Issue
Block a user