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fpga: lib: Allow buffering in eth_ipv4_chdr_adapter

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Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.


Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
This commit is contained in:
Wade Fife
2023-10-18 22:23:55 -05:00
parent 613444b39b
commit e4d9a9a448
1 changed files with 6 additions and 2 deletions
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lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
+5 -1
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@@ -319,7 +319,11 @@ module eth_ipv4_chdr_adapter #(
// Adding so packet will be contiguous going out // Adding so packet will be contiguous going out
// The MAC needs bandwidth feeding it to be greater than the line rate // The MAC needs bandwidth feeding it to be greater than the line rate
if (ENET_W > CHDR_W || !SYNC) begin : gen_v2e_packet_gate if (ENET_W > CHDR_W || !SYNC) begin : gen_v2e_packet_gate
axi4s_packet_gate #(.SIZE(17-$clog2(ENET_W)), .USE_AS_BUFF(0)) // Set gate depth to 16 KiB
localparam SIZE = 17-$clog2(ENET_W);
// Buffer up to 2**N packets, by setting MIN_PKT_SIZE to SIZE-N.
localparam MIN_PKT_SIZE = SIZE-5;
axi4s_packet_gate #(.SIZE(SIZE), .USE_AS_BUFF(1), .MIN_PKT_SIZE(MIN_PKT_SIZE))
v2e_gate_i (.clear(1'b0),.error(1'b0),.i(v2e2),.o(v2e3)); v2e_gate_i (.clear(1'b0),.error(1'b0),.i(v2e2),.o(v2e3));
end else begin : gen_v2e_no_packet_gate end else begin : gen_v2e_no_packet_gate
always_comb begin : v2e1_assign always_comb begin : v2e1_assign