From e4d9a9a44840eb8a70617490db72e2d1dd810134 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 11 Oct 2023 13:15:42 -0500 Subject: [PATCH] fpga: lib: Allow buffering in eth_ipv4_chdr_adapter Enable USE_AS_BUFF on packet gate to allow many packets to be buffered. This reduces latency when several small packets are sent out close together. Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68 --- lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv b/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv index 0f5abf5..cf2b98e 100644 --- a/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv +++ b/lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv @@ -319,8 +319,12 @@ module eth_ipv4_chdr_adapter #( // Adding so packet will be contiguous going out // The MAC needs bandwidth feeding it to be greater than the line rate if (ENET_W > CHDR_W || !SYNC) begin : gen_v2e_packet_gate - axi4s_packet_gate #(.SIZE(17-$clog2(ENET_W)), .USE_AS_BUFF(0)) - v2e_gate_i (.clear(1'b0),.error(1'b0),.i(v2e2),.o(v2e3)); + // Set gate depth to 16 KiB + localparam SIZE = 17-$clog2(ENET_W); + // Buffer up to 2**N packets, by setting MIN_PKT_SIZE to SIZE-N. + localparam MIN_PKT_SIZE = SIZE-5; + axi4s_packet_gate #(.SIZE(SIZE), .USE_AS_BUFF(1), .MIN_PKT_SIZE(MIN_PKT_SIZE)) + v2e_gate_i (.clear(1'b0),.error(1'b0),.i(v2e2),.o(v2e3)); end else begin : gen_v2e_no_packet_gate always_comb begin : v2e1_assign `AXI4S_ASSIGN(v2e3,v2e2)