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fpga: x400: Use x410_200 image core for x410_100 images

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Original-commit: 23c856d4d9152153e34699e7507c4363c99b6124
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent 7fa7ce1f81
commit dd2b935f4b
5 changed files with 3 additions and 1879 deletions
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top/x400/Makefile
+3 -4
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@@ -71,7 +71,6 @@ BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED) DEFS += BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets: # Defaults specific to the various targets:
X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex) X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex) X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex) X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
@@ -125,15 +124,15 @@ endif
##* Note: Not all targets are shipped with UHD ##* Note: Not all targets are shipped with UHD
X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X1_100) $(call post_build,X410,X1_100)
X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,XG_100) $(call post_build,X410,XG_100)
X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_100) $(call post_build,X410,X4_100)
X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
top/x400/x410_100_rfnoc_image_core.v
-1675
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File diff suppressed because it is too large Load Diff
top/x400/x410_100_rfnoc_image_core.vh
-21
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@@ -1,21 +0,0 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-04-05T20:50:53.089049
// Source: ./x410_100_rfnoc_image_core.yml
// Source SHA256: 73ccfd5525b2438c74beb7694091d456ae10bff92ceaab68946dd8b00a052ea0
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_100_rfnoc_image_core.yml
-154
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@@ -1,154 +0,0 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'x410_100' # Name to use for the RFNoC Image Core files
default_target: 'X410_XG_100' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size_bytes: 262144
ep2:
ctrl: False
data: True
buff_size_bytes: 262144
ep3:
ctrl: False
data: True
buff_size_bytes: 262144
ep4:
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 2
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
duc1:
block_desc: 'duc.yml'
parameters:
NUM_PORTS: 2
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 4
MEM_DATA_W: 64
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_100_static_router.hex
-25
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@@ -1,25 +0,0 @@
00000018
00400240
024002c0
02c00280
02800040
00800241
024102c1
02c10281
02810080
00c00300
03000380
03800340
034000c0
01000301
03010381
03810341
03410100
014003c0
03c00140
018003c1
03c10180
01c003c2
03c201c0
020003c3
03c30200