miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: lib: Fix addsub_hls

Browse Source 
Original-commit: f3e28c36a0e37341038370856ab2babd1dff0b3b
This commit is contained in:
Wade Fife
2022-08-25 13:55:30 -05:00
committed by skooNI
parent b6d9977685
commit dd1e980463
1 changed files with 34 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/hls/addsub_hls/addsub_hls.cpp
+34 -33
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2022 Ettus Research, a National Instruments Company // Copyright 2022 Ettus Research, a National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -9,43 +9,44 @@
#include <complex> #include <complex>
typedef std::complex<short int> axis_data; typedef std::complex<short int> axis_data;
typedef hls::axis<axis_data, 0, 0, 0> trans_pkt; typedef hls::axis<axis_data, 0, 0, 0> axis_cplx;
// AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only // The AXI-Stream port type is compatible with pointer, reference, array, and
// See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49 // stream input/outputs only. See UG902 Vivado High Level Synthesis guide for
void addsub_hls(hls::stream<trans_pkt>& a, // details.
hls::stream<trans_pkt>& b, void addsub_hls(
hls::stream<trans_pkt>& add, hls::stream<axis_cplx>& a,
hls::stream<trans_pkt>& sub) hls::stream<axis_cplx>& b,
hls::stream<axis_cplx>& add,
hls::stream<axis_cplx>& sub)
{ {
// Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only
// AXI-Stream ports // use the AXI-Stream ports.
#pragma HLS INTERFACE ap_ctrl_none port = return #pragma HLS INTERFACE ap_ctrl_none port = return
// Set ports as AXI-Stream // Set ports as AXI-Stream
#pragma HLS INTERFACE axis port = sub #pragma HLS INTERFACE axis port = sub
#pragma HLS INTERFACE axis port = add #pragma HLS INTERFACE axis port = add
#pragma HLS INTERFACE axis port = a #pragma HLS INTERFACE axis port = a
#pragma HLS INTERFACE axis port = b #pragma HLS INTERFACE axis port = b
// Complex add / subtract // Pipeline with initiation interval of 1 clock cycle
trans_pkt a_pkt; #pragma HLS PIPELINE II=1
a.read(a_pkt);
trans_pkt b_pkt; // Read the next pair of AXI-stream inputs
b.read(b_pkt); axis_cplx a_trans, b_trans;
a.read(a_trans);
b.read(b_trans);
trans_pkt add_pkt; // Complex addition
add_pkt.data = { axis_cplx add_trans;
a_pkt.data.real() + b_pkt.data.real(), add_trans.data = a_trans.data + b_trans.data;
a_pkt.data.imag() + b_pkt.data.imag()}; add_trans.last = a_trans.last;
add_pkt.last = a_pkt.last; add.write(add_trans);
add.write(add_pkt);
trans_pkt sub_pkt; // Complex subtraction
sub_pkt.data = { axis_cplx sub_trans;
a_pkt.data.real() - b_pkt.data.real(), sub_trans.data = a_trans.data - b_trans.data;
a_pkt.data.imag() - b_pkt.data.imag()}; sub_trans.last = a_trans.last;
sub_pkt.last = a_pkt.last; sub.write(sub_trans);
sub.write(sub_pkt);
} }