From dd1e980463f96815a2baef03c99f00c36275bfbf Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Wed, 15 Jun 2022 18:08:52 -0500
Subject: [PATCH] fpga: lib: Fix addsub_hls

Original-commit: f3e28c36a0e37341038370856ab2babd1dff0b3b
---
 lib/hls/addsub_hls/addsub_hls.cpp | 67 ++++++++++++++++---------------
 1 file changed, 34 insertions(+), 33 deletions(-)

diff --git a/lib/hls/addsub_hls/addsub_hls.cpp b/lib/hls/addsub_hls/addsub_hls.cpp
index 1d9d7ea..934635c 100644
--- a/lib/hls/addsub_hls/addsub_hls.cpp
+++ b/lib/hls/addsub_hls/addsub_hls.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2022 Ettus Research, a National Instruments Company
+// Copyright 2022 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -9,43 +9,44 @@
 #include <complex>
 
 typedef std::complex<short int> axis_data;
-typedef hls::axis<axis_data, 0, 0, 0> trans_pkt;
+typedef hls::axis<axis_data, 0, 0, 0> axis_cplx;
 
-// AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only
-// See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49
-void addsub_hls(hls::stream<trans_pkt>& a,
-    hls::stream<trans_pkt>& b,
-    hls::stream<trans_pkt>& add,
-    hls::stream<trans_pkt>& sub)
+// The AXI-Stream port type is compatible with pointer, reference, array, and
+// stream input/outputs only. See UG902 Vivado High Level Synthesis guide for
+// details.
+void addsub_hls(
+    hls::stream<axis_cplx>& a,
+    hls::stream<axis_cplx>& b,
+    hls::stream<axis_cplx>& add,
+    hls::stream<axis_cplx>& sub)
 {
-	// Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the
-	// AXI-Stream ports
-	#pragma HLS INTERFACE ap_ctrl_none port = return
+    // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only
+    // use the AXI-Stream ports.
+    #pragma HLS INTERFACE ap_ctrl_none port = return
 
-	// Set ports as AXI-Stream
-	#pragma HLS INTERFACE axis port = sub
-	#pragma HLS INTERFACE axis port = add
-	#pragma HLS INTERFACE axis port = a
-	#pragma HLS INTERFACE axis port = b
+    // Set ports as AXI-Stream
+    #pragma HLS INTERFACE axis port = sub
+    #pragma HLS INTERFACE axis port = add
+    #pragma HLS INTERFACE axis port = a
+    #pragma HLS INTERFACE axis port = b
 
-    // Complex add / subtract
-    trans_pkt a_pkt;
-    a.read(a_pkt);
+    // Pipeline with initiation interval of 1 clock cycle
+    #pragma HLS PIPELINE II=1
 
-    trans_pkt b_pkt;
-    b.read(b_pkt);
+    // Read the next pair of AXI-stream inputs
+    axis_cplx a_trans, b_trans;
+    a.read(a_trans);
+    b.read(b_trans);
 
-    trans_pkt add_pkt;
-    add_pkt.data = {
-        a_pkt.data.real() + b_pkt.data.real(),
-		a_pkt.data.imag() + b_pkt.data.imag()};
-    add_pkt.last = a_pkt.last;
-    add.write(add_pkt);
+    // Complex addition
+    axis_cplx add_trans;
+    add_trans.data = a_trans.data + b_trans.data;
+    add_trans.last = a_trans.last;
+    add.write(add_trans);
 
-    trans_pkt sub_pkt;
-    sub_pkt.data = {
-        a_pkt.data.real() - b_pkt.data.real(),
-		a_pkt.data.imag() - b_pkt.data.imag()};
-    sub_pkt.last = a_pkt.last;
-    sub.write(sub_pkt);
+    // Complex subtraction
+    axis_cplx sub_trans;
+    sub_trans.data = a_trans.data - b_trans.data;
+    sub_trans.last = a_trans.last;
+    sub.write(sub_trans);
 }