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DUC/DDC: Add variable time increment

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Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample.  Defaults to legacy behavior.

Minor compat number bumped on DUC and DDC blocks.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
This commit is contained in:
Michael West
2020-05-12 12:03:31 -05:00
committed by Aaron Rossetto
parent 45d274746f
commit dc86b52fd7
5 changed files with 39 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc.v
+4 -2
View File
@@ -1,5 +1,6 @@
//
// Copyright 2019 Ettus Research, a National Instruments Company
// Copyright 2020 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -73,7 +74,7 @@ module rfnoc_block_duc #(
localparam NIPC = 1;
localparam COMPAT_MAJOR = 16'h0;
localparam COMPAT_MINOR = 16'h0;
localparam COMPAT_MINOR = 16'h1;
`include "rfnoc_block_duc_regs.vh"
`include "../../core/rfnoc_axis_ctrl_utils.vh"
@@ -316,7 +317,8 @@ module rfnoc_block_duc #(
.MAX_M(MAX_M),
.SR_N_ADDR(SR_N_ADDR),
.SR_M_ADDR(SR_M_ADDR),
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
.SR_CONFIG_ADDR(SR_CONFIG_ADDR),
.SR_TIME_INCR_ADDR(SR_TIME_INCR_ADDR))
axi_rate_change (
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_regs.vh
+2 -1
View File
@@ -1,5 +1,6 @@
//
// Copyright 2019 Ettus Research, A National Instruments Company
// Copyright 2020 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -22,4 +23,4 @@ localparam SR_CONFIG_ADDR = 130;
localparam SR_INTERP_ADDR = 131;
localparam SR_FREQ_ADDR = 132;
localparam SR_SCALE_IQ_ADDR = 133;
localparam SR_TIME_INCR_ADDR = 137;