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fpga: Added FPGA code for B200 AD9361 host driver addition

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Original-commit: 9fb6c2919ad9e7e736c837186861b362ba80cdfa
This commit is contained in:
Ashish Chaudhari
2014-08-20 09:31:33 -07:00
parent 6b7004c311
commit d8650bce9b
2 changed files with 19 additions and 8 deletions
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top/b200/b200.v
+17 -6
View File
@@ -179,16 +179,27 @@ module b200 (
///////////////////////////////////////////////////////////////////////
// SPI connections
///////////////////////////////////////////////////////////////////////
wire mosi, miso, sclk; wire [7:0] sen;
assign cat_ce = sen[0] & fx3_ce;
assign cat_mosi = (~sen[0] & mosi) | (~fx3_ce & fx3_mosi);
assign cat_sclk = (~sen[0] & sclk) | (~fx3_ce & fx3_sclk);
assign miso = cat_miso;
assign fx3_miso = ~fx3_ce & cat_miso;
wire mosi, miso, sclk;
wire [7:0] sen;
//AD9361 Slave
assign cat_ce = sen[0];
assign cat_mosi = ~sen[0] & mosi;
assign cat_sclk = ~sen[0] & sclk;
assign miso = cat_miso; //PLL does not have a miso
//ADF4001 Slave
assign pll_ce = sen[1];
assign pll_mosi = ~sen[1] & mosi;
assign pll_sclk = ~sen[1] & sclk;
//FX3 Master
//The following signals are routed to the FX3 and were used by an obsolete
//bit-banging SPI engine.
// fx3_ce, fx3_sclk, fx3_mosi <Unused>
assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
//direction of this pin in the FX3
///////////////////////////////////////////////////////////////////////
// bus signals
///////////////////////////////////////////////////////////////////////
top/b200/b200_core.v
+1 -1
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@@ -72,7 +72,7 @@ module b200_core
localparam SR_CORE_READBACK = 8'd32;
localparam SR_CORE_GPSDO_ST = 8'd40;
localparam SR_CORE_PPS_SEL = 8'd48;
localparam COMPAT_MAJOR = 16'h0003;
localparam COMPAT_MAJOR = 16'h0004;
localparam COMPAT_MINOR = 16'h0000;
/*******************************************************************