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fpga: x4xx: add reset option for gearboxes

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Original-commit: 22b4a35da29fd70a6a6030e555139b4bb7cc56f1
This commit is contained in:
Max Köhler
2025-04-02 08:02:11 +02:00
committed by Jörg Hofrichter
parent 14e864bdb1
commit d742b4018f
3 changed files with 92 additions and 22 deletions
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top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
+12
View File
@@ -144,6 +144,12 @@
// db0_adc_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="ADC_GEARBOX_RESET" range="6">
// <info>
// Write a '1' to this bit to trigger a reset for the ADC gearboxes.
// There is no done signal for this reset.
// </info>
// </bitfield>
// <bitfield name="DAC_RESET" range="8">
// <info>
// Write a '1' to this bit to trigger a reset for the
@@ -158,6 +164,12 @@
// db0_dac_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_GEARBOX_RESET" range="10">
// <info>
// Write a '1' to this bit to trigger a reset for the DAC gearboxes.
// There is no done signal for this reset.
// </info>
// </bitfield>
// </regtype>
//
// <regtype name="RF_RESET_STATUS_REGTYPE" size="32" writable="false">
top/x400/regmap/x410/PkgRFDC_REGS_REGMAP.vhd
+7 -1
View File
@@ -223,7 +223,7 @@ package PkgRFDC_REGS_REGMAP is
-- RF_RESET_CONTROL_REGTYPE Type (from common_regs.v)
constant kRF_RESET_CONTROL_REGTYPESize: integer := 32;
constant kRF_RESET_CONTROL_REGTYPEMask : std_logic_vector(31 downto 0) := X"00000331";
constant kRF_RESET_CONTROL_REGTYPEMask : std_logic_vector(31 downto 0) := X"00000771";
constant kFSM_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:FSM_RESET
constant kFSM_RESETMsb : integer := 0; --RF_RESET_CONTROL_REGTYPE:FSM_RESET
constant kFSM_RESET : integer := 0; --RF_RESET_CONTROL_REGTYPE:FSM_RESET
@@ -233,12 +233,18 @@ package PkgRFDC_REGS_REGMAP is
constant kADC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
constant kADC_ENABLEMsb : integer := 5; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
constant kADC_ENABLE : integer := 5; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
constant kADC_GEARBOX_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:ADC_GEARBOX_RESET
constant kADC_GEARBOX_RESETMsb : integer := 6; --RF_RESET_CONTROL_REGTYPE:ADC_GEARBOX_RESET
constant kADC_GEARBOX_RESET : integer := 6; --RF_RESET_CONTROL_REGTYPE:ADC_GEARBOX_RESET
constant kDAC_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:DAC_RESET
constant kDAC_RESETMsb : integer := 8; --RF_RESET_CONTROL_REGTYPE:DAC_RESET
constant kDAC_RESET : integer := 8; --RF_RESET_CONTROL_REGTYPE:DAC_RESET
constant kDAC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
constant kDAC_ENABLEMsb : integer := 9; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
constant kDAC_ENABLE : integer := 9; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
constant kDAC_GEARBOX_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:DAC_GEARBOX_RESET
constant kDAC_GEARBOX_RESETMsb : integer := 10; --RF_RESET_CONTROL_REGTYPE:DAC_GEARBOX_RESET
constant kDAC_GEARBOX_RESET : integer := 10; --RF_RESET_CONTROL_REGTYPE:DAC_GEARBOX_RESET
-- RF_RESET_STATUS_REGTYPE Type (from common_regs.v)
constant kRF_RESET_STATUS_REGTYPESize: integer := 32;
top/x400/rf/x410/x410_rf_reset_controller.vhd
+54 -2
View File
@@ -57,6 +57,19 @@ end x410_rf_reset_controller;
architecture RTL of x410_rf_reset_controller is
component pulse_synchronizer
generic (
MODE : string := "PULSE";
STAGES : integer := 2);
port (
clk_a : in std_logic;
rst_a : in std_logic;
pulse_a : in std_logic;
busy_a : out std_logic;
clk_b : in std_logic;
pulse_b : out std_logic);
end component;
-- POR value for all resets are high.
signal cTriggerAdcReset : std_logic := '1';
signal cTriggerAdcResetDlyd : std_logic := '1';
@@ -86,6 +99,12 @@ architecture RTL of x410_rf_reset_controller is
attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
signal cTriggerAdcGearboxReset : std_logic;
signal cTriggerDacGearboxReset : std_logic;
signal dTriggerAdcGearboxReset : std_logic;
signal dTriggerDacGearboxReset : std_logic;
begin
-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
@@ -93,6 +112,8 @@ begin
cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
cTriggerAdcGearboxReset <= cSoftwareControl(kADC_GEARBOX_RESET);
cTriggerDacGearboxReset <= cSoftwareControl(kDAC_GEARBOX_RESET);
cSoftwareStatus <= (
kADC_SEQ_DONE => cAdcResetDoneSticky,
@@ -169,6 +190,37 @@ begin
end if;
end process SwDacResetDone;
-----------------------------------------------------------------------------
-- transfer posedge gearbox triggers to DataClk domain
-----------------------------------------------------------------------------
adc_gearbox_reset_pulse_sync : pulse_synchronizer
generic map (
MODE => "POSEDGE",
STAGES => 2
)
port map (
clk_a => ConfigClk,
rst_a => '0',
pulse_a => cTriggerAdcGearboxReset,
busy_a => open,
clk_b => DataClk,
pulse_b => dTriggerAdcGearboxReset
);
dac_gearbox_reset_pulse_sync : pulse_synchronizer
generic map (
MODE => "POSEDGE",
STAGES => 2
)
port map (
clk_a => ConfigClk,
rst_a => '0',
pulse_a => cTriggerDacGearboxReset,
busy_a => open,
clk_b => DataClk,
pulse_b => dTriggerDacGearboxReset
);
-----------------------------------------------------------------------------
-- rf_reset Instances
-----------------------------------------------------------------------------
@@ -180,7 +232,7 @@ begin
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dAdcResetPulse,
dTimedReset => (dAdcResetPulse or dTriggerAdcGearboxReset),
dSwReset => dTriggerAdcReset,
dReset_n => dAdcDataOutReset_n,
d2Reset_n => open,
@@ -196,7 +248,7 @@ begin
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dDacResetPulse,
dTimedReset => (dDacResetPulse or dTriggerDacGearboxReset),
dSwReset => dTriggerDacReset,
dReset_n => dDacDataInReset_n,
d2Reset_n => d2DacFirReset_n,