miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: x4xx: add reset option for gearboxes

Browse Source 
Original-commit: 22b4a35da29fd70a6a6030e555139b4bb7cc56f1
This commit is contained in:
Max Köhler
2025-04-02 08:02:11 +02:00
committed by Jörg Hofrichter
parent 14e864bdb1
commit d742b4018f
3 changed files with 92 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/rf/x410/x410_rf_reset_controller.vhd
+56 -4
View File
@@ -57,6 +57,19 @@ end x410_rf_reset_controller;
architecture RTL of x410_rf_reset_controller is
component pulse_synchronizer
generic (
MODE : string := "PULSE";
STAGES : integer := 2);
port (
clk_a : in std_logic;
rst_a : in std_logic;
pulse_a : in std_logic;
busy_a : out std_logic;
clk_b : in std_logic;
pulse_b : out std_logic);
end component;
-- POR value for all resets are high.
signal cTriggerAdcReset : std_logic := '1';
signal cTriggerAdcResetDlyd : std_logic := '1';
@@ -86,13 +99,21 @@ architecture RTL of x410_rf_reset_controller is
attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
signal cTriggerAdcGearboxReset : std_logic;
signal cTriggerDacGearboxReset : std_logic;
signal dTriggerAdcGearboxReset : std_logic;
signal dTriggerDacGearboxReset : std_logic;
begin
-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
rAdcEnableData <= '1';
cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
cTriggerAdcGearboxReset <= cSoftwareControl(kADC_GEARBOX_RESET);
cTriggerDacGearboxReset <= cSoftwareControl(kDAC_GEARBOX_RESET);
cSoftwareStatus <= (
kADC_SEQ_DONE => cAdcResetDoneSticky,
@@ -169,6 +190,37 @@ begin
end if;
end process SwDacResetDone;
-----------------------------------------------------------------------------
-- transfer posedge gearbox triggers to DataClk domain
-----------------------------------------------------------------------------
adc_gearbox_reset_pulse_sync : pulse_synchronizer
generic map (
MODE => "POSEDGE",
STAGES => 2
)
port map (
clk_a => ConfigClk,
rst_a => '0',
pulse_a => cTriggerAdcGearboxReset,
busy_a => open,
clk_b => DataClk,
pulse_b => dTriggerAdcGearboxReset
);
dac_gearbox_reset_pulse_sync : pulse_synchronizer
generic map (
MODE => "POSEDGE",
STAGES => 2
)
port map (
clk_a => ConfigClk,
rst_a => '0',
pulse_a => cTriggerDacGearboxReset,
busy_a => open,
clk_b => DataClk,
pulse_b => dTriggerDacGearboxReset
);
-----------------------------------------------------------------------------
-- rf_reset Instances
-----------------------------------------------------------------------------
@@ -180,7 +232,7 @@ begin
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dAdcResetPulse,
dTimedReset => (dAdcResetPulse or dTriggerAdcGearboxReset),
dSwReset => dTriggerAdcReset,
dReset_n => dAdcDataOutReset_n,
d2Reset_n => open,
@@ -196,7 +248,7 @@ begin
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dDacResetPulse,
dTimedReset => (dDacResetPulse or dTriggerDacGearboxReset),
dSwReset => dTriggerDacReset,
dReset_n => dDacDataInReset_n,
d2Reset_n => d2DacFirReset_n,