FPGA: Add time changed pulse to timekeeper

The time changed signal was removed and is needed to synchronized the
frontend.  This restores the signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
This commit is contained in:
michael-west
2023-05-10 14:22:42 -05:00
committed by Wade Fife
parent e49258d910
commit d6bcab7c8c
+7 -2
View File
@@ -33,6 +33,7 @@
// tb_timestamp : 64-bit global timestamp synchronous to tb_clk // tb_timestamp : 64-bit global timestamp synchronous to tb_clk
// tb_timestamp_last_pps : 64-bit timestamp of the last PPS edge // tb_timestamp_last_pps : 64-bit timestamp of the last PPS edge
// tb_period_ns_q32 : Time Period of time-base in nanoseconds // tb_period_ns_q32 : Time Period of time-base in nanoseconds
// tb_changed : Pulse indicating the time-base has changed
// //
module timekeeper #( module timekeeper #(
@@ -63,7 +64,8 @@ module timekeeper #(
input wire pps, input wire pps,
output reg [63:0] tb_timestamp, output reg [63:0] tb_timestamp,
output reg [63:0] tb_timestamp_last_pps, output reg [63:0] tb_timestamp_last_pps,
output reg [63:0] tb_period_ns_q32 output reg [63:0] tb_period_ns_q32,
output reg tb_changed
); );
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
@@ -267,14 +269,17 @@ module timekeeper #(
if (tb_rst) begin if (tb_rst) begin
tb_timestamp <= 0; tb_timestamp <= 0;
time_event_armed <= 0; time_event_armed <= 0;
tb_changed <= 0;
end else begin end else begin
tb_changed <= 0;
if (time_event) begin if (time_event) begin
// Load the timing info configured prior to the event // Load the timing info configured prior to the event
time_event_armed <= 0; time_event_armed <= 0;
tb_timestamp <= time_at_next_event; tb_timestamp <= time_at_next_event;
tb_changed <= 1;
end else if (sample_rx_stb) begin end else if (sample_rx_stb) begin
// Update time for each sample word received // Update time for each sample word received
tb_timestamp <= tb_timestamp + increment; tb_timestamp <= tb_timestamp + increment;
end end
if (new_time_ctrl) begin if (new_time_ctrl) begin