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fpga: lib: rfnoc: Make RFNoC packet gates removable

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This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output
to make their packet gates optional. They are included by default.

Having the packet gate in chdr_xb_ingress_buff can reduce contention in
the crossbar. Having the packet gate in chdr_stream_output can reduce
the latency for non-data packets (e.g., stream status updates).


Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
This commit is contained in:
Wade Fife
2023-02-24 08:07:17 -06:00
parent fd87d4cf30
commit d671f408c0
2 changed files with 77 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/core/chdr_stream_output.v
+27 -9
View File
@@ -15,8 +15,9 @@
// configuration bus to initiate stream creation.
//
// Parameters:
// - CHDR_W: Width of the CHDR bus in bits
// - MTU: Log2 of the maximum number of lines in a packet
// - CHDR_W : Width of the CHDR bus in bits
// - MTU : Log2 of the maximum number of lines in a packet
// - EN_PKT_GATE : Enable packet gate to make each packet contiguous
//
// Signals:
// - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
@@ -25,7 +26,8 @@
module chdr_stream_output #(
parameter CHDR_W = 256,
parameter MTU = 10
parameter MTU = 10,
parameter EN_PKT_GATE = 1
)(
// Clock, reset and settings
input wire clk,
@@ -84,15 +86,31 @@ module chdr_stream_output #(
reg chdr_out_tlast, chdr_out_tvalid;
wire chdr_out_tready;
if (EN_PKT_GATE) begin : gen_pkt_gate
axi_packet_gate #(
.WIDTH(CHDR_W), .SIZE(MTU), .USE_AS_BUFF(0)
.WIDTH (CHDR_W),
.SIZE (MTU ),
.USE_AS_BUFF(0 )
) chdr_pkt_gate_i (
.clk(clk), .reset(rst), .clear(1'b0),
.i_tdata(chdr_out_tdata), .i_tlast(chdr_out_tlast), .i_terror(1'b0),
.i_tvalid(chdr_out_tvalid), .i_tready(chdr_out_tready),
.o_tdata(m_axis_chdr_tdata), .o_tlast(m_axis_chdr_tlast),
.o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
.clk (clk ),
.reset (rst ),
.clear (1'b0 ),
.i_tdata (chdr_out_tdata ),
.i_tlast (chdr_out_tlast ),
.i_terror(1'b0 ),
.i_tvalid(chdr_out_tvalid ),
.i_tready(chdr_out_tready ),
.o_tdata (m_axis_chdr_tdata ),
.o_tlast (m_axis_chdr_tlast ),
.o_tvalid(m_axis_chdr_tvalid),
.o_tready(m_axis_chdr_tready)
);
end else begin : gen_no_pkt_gate
assign m_axis_chdr_tdata = chdr_out_tdata;
assign m_axis_chdr_tlast = chdr_out_tlast;
assign m_axis_chdr_tvalid = chdr_out_tvalid;
assign chdr_out_tready = m_axis_chdr_tready;
end
// ---------------------------------------------------
// Flow Control State
lib/rfnoc/crossbar/chdr_xb_ingress_buff.v
+22 -1
View File
@@ -18,13 +18,16 @@
// MTU : Maximum transmission unit, in WIDTH-sized words, is 2**MTU
// DEST_W : Width of the destination routing information (TDEST)
// NODE_ID : Numeric identifier for this port
// EN_PKT_GATE : Enable packet gate to make each packet contiguous. This
// reduces congestion in the crossbar.
//
module chdr_xb_ingress_buff #(
parameter WIDTH = 64,
parameter MTU = 10,
parameter DEST_W = 4,
parameter [9:0] NODE_ID = 0
parameter [9:0] NODE_ID = 0,
parameter EN_PKT_GATE = 1
) (
input wire clk,
input wire reset,
@@ -69,6 +72,7 @@ module chdr_xb_ingress_buff #(
// The axi_packet_gate queues up an entire packet before letting it go out.
// This reduces congestion in the crossbar for slowly-built packets.
if (EN_PKT_GATE) begin : gen_pkt_gate
axi_packet_gate #(
.WIDTH (WIDTH),
.SIZE (MTU)
@@ -86,6 +90,23 @@ module chdr_xb_ingress_buff #(
.o_tvalid (gate_o_tvalid),
.o_tready (gate_o_tready)
);
end else begin : gen_no_pkt_gate
axi_fifo_flop2 #(
.WIDTH(WIDTH+1)
) axi_fifo_flop2_i (
.clk (clk ),
.reset (reset ),
.clear (1'b0 ),
.i_tdata ({gate_i_tlast, gate_i_tdata}),
.i_tvalid(gate_i_tvalid ),
.i_tready(gate_i_tready ),
.o_tdata ({gate_o_tlast, gate_o_tdata}),
.o_tvalid(gate_o_tvalid ),
.o_tready(gate_o_tready ),
.space ( ),
.occupied( )
);
end
//---------------------------------------------------------------------------