Wade Fife
d671f408c0
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output to make their packet gates optional. They are included by default. Having the packet gate in chdr_xb_ingress_buff can reduce contention in the crossbar. Having the packet gate in chdr_stream_output can reduce the latency for non-data packets (e.g., stream status updates). Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
281 lines
10 KiB
Verilog
281 lines
10 KiB
Verilog
//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_ingress_buff
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//
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// Description:
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//
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// Ingress buffer module for the CHDR crossbar. This module stores and gates
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// the incoming packet and simultaneously determines the destination (TDEST)
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// by inspecting the incoming TID. If the TID is CHDR_MGMT_ROUTE_EPID then we
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// perform a lookup on the TID to determine the correct output for TDEST.
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//
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// Parameters:
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//
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// WIDTH : Data width of the CHDR interfaces (TDATA)
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// MTU : Maximum transmission unit, in WIDTH-sized words, is 2**MTU
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// DEST_W : Width of the destination routing information (TDEST)
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// NODE_ID : Numeric identifier for this port
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// EN_PKT_GATE : Enable packet gate to make each packet contiguous. This
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// reduces congestion in the crossbar.
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//
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module chdr_xb_ingress_buff #(
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parameter WIDTH = 64,
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parameter MTU = 10,
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parameter DEST_W = 4,
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parameter [9:0] NODE_ID = 0,
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parameter EN_PKT_GATE = 1
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) (
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input wire clk,
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input wire reset,
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// CHDR input port
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input wire [WIDTH-1:0] s_axis_chdr_tdata,
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input wire [DEST_W-1:0] s_axis_chdr_tdest,
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input wire [1:0] s_axis_chdr_tid,
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input wire s_axis_chdr_tlast,
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input wire s_axis_chdr_tvalid,
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output wire s_axis_chdr_tready,
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// CHDR output port (with a tdest and tkeep)
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output wire [WIDTH-1:0] m_axis_chdr_tdata,
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output wire [DEST_W-1:0] m_axis_chdr_tdest,
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output wire m_axis_chdr_tkeep,
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output wire m_axis_chdr_tlast,
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output wire m_axis_chdr_tvalid,
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input wire m_axis_chdr_tready,
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// Find port going to routing table
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output wire [15:0] m_axis_find_tdata,
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output wire m_axis_find_tvalid,
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input wire m_axis_find_tready,
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// Result port from routing table
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input wire [DEST_W-1:0] s_axis_result_tdata,
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input wire s_axis_result_tkeep,
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input wire s_axis_result_tvalid,
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output wire s_axis_result_tready
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);
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// RFNoC Includes
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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//---------------------------------------------------------------------------
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// Packet Buffer
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//---------------------------------------------------------------------------
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wire [WIDTH-1:0] gate_i_tdata , gate_o_tdata ;
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wire gate_i_tlast , gate_o_tlast ;
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wire gate_i_tvalid, gate_o_tvalid;
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wire gate_i_tready, gate_o_tready;
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// The axi_packet_gate queues up an entire packet before letting it go out.
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// This reduces congestion in the crossbar for slowly-built packets.
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if (EN_PKT_GATE) begin : gen_pkt_gate
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axi_packet_gate #(
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.WIDTH (WIDTH),
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.SIZE (MTU)
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) axi_packet_gate_i (
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.clk (clk),
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.reset (reset),
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.clear (1'b0),
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.i_tdata (gate_i_tdata),
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.i_tlast (gate_i_tlast),
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.i_terror (1'b0),
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.i_tvalid (gate_i_tvalid),
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.i_tready (gate_i_tready),
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.o_tdata (gate_o_tdata),
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.o_tlast (gate_o_tlast),
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.o_tvalid (gate_o_tvalid),
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.o_tready (gate_o_tready)
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);
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end else begin : gen_no_pkt_gate
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axi_fifo_flop2 #(
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.WIDTH(WIDTH+1)
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) axi_fifo_flop2_i (
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.clk (clk ),
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.reset (reset ),
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.clear (1'b0 ),
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.i_tdata ({gate_i_tlast, gate_i_tdata}),
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.i_tvalid(gate_i_tvalid ),
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.i_tready(gate_i_tready ),
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.o_tdata ({gate_o_tlast, gate_o_tdata}),
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.o_tvalid(gate_o_tvalid ),
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.o_tready(gate_o_tready ),
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.space ( ),
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.occupied( )
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);
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end
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//---------------------------------------------------------------------------
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// Destination (TDEST) Muxing
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//---------------------------------------------------------------------------
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wire [15:0] find_tdata;
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wire find_tvalid, find_tready;
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wire [DEST_W-1:0] dest_i_tdata;
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wire dest_i_tkeep, dest_i_tvalid, dest_i_tready;
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wire [DEST_W-1:0] dest_o_tdata;
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wire dest_o_tkeep, dest_o_tvalid, dest_o_tready;
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// The find_fifo holds the lookup requests from the find_* AXI stream and
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// sends them on to the m_axis_find_* stream port. It is required because the
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// input logic (see below) doesn't obey the AXI handshake protocol but this
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// FIFO can tolerate it.
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axi_fifo #(
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.WIDTH (16),
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.SIZE (1)
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) find_fifo_i (
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.clk (clk),
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.reset (reset),
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.clear (1'b0),
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.i_tdata (find_tdata),
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.i_tvalid (find_tvalid),
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.i_tready (find_tready),
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.o_tdata (m_axis_find_tdata),
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.o_tvalid (m_axis_find_tvalid),
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.o_tready (m_axis_find_tready),
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.space (),
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.occupied ()
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);
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// The destination (TDEST) can come from two sources: Directly from the
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// packet info (in which case TDEST was immediately determined and comes in
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// on dest_* AXI stream) or via a lookup (in which case the result comes in
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// on s_axis_result_*). Only one of these data paths is used at a time, so we
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// mux them together here create a single stream (dest_o_*) that contains the
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// destination for the next packet.
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axi_mux #(
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.WIDTH (DEST_W+1),
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.SIZE (2),
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.PRIO (1),
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.PRE_FIFO_SIZE (1),
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.POST_FIFO_SIZE (1)
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) dest_mux_i (
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.clk (clk),
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.reset (reset),
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.clear (1'b0),
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.i_tdata ({dest_i_tkeep, dest_i_tdata,
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s_axis_result_tkeep, s_axis_result_tdata}),
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.i_tlast (2'b11),
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.i_tvalid ({dest_i_tvalid, s_axis_result_tvalid}),
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.i_tready ({dest_i_tready, s_axis_result_tready}),
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.o_tdata ({dest_o_tkeep, dest_o_tdata}),
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.o_tlast (),
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.o_tvalid (dest_o_tvalid),
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.o_tready (dest_o_tready)
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);
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//---------------------------------------------------------------------------
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// Input Logic
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//---------------------------------------------------------------------------
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//
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// When a packet comes in, we may have to do one of the following:
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// 1) Lookup the TDEST using the EPID
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// 2) Use the specified input TDEST
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// 3) Use the NODE_ID as the TDEST (to return the packet)
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//
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//---------------------------------------------------------------------------
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// The s_axis_chdr_hdr_valid signal indicates when TDATA and TID contain the
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// header information for the current packet.
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reg s_axis_chdr_hdr_valid = 1'b1;
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always @(posedge clk) begin
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if (reset) begin
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s_axis_chdr_hdr_valid <= 1'b1;
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end else if (s_axis_chdr_tvalid & s_axis_chdr_tready) begin
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s_axis_chdr_hdr_valid <= s_axis_chdr_tlast;
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end
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end
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// The dest_find_tready signal indicates if the find_fifo is ready or if the
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// dest port of the dest_muax is ready, depending on which path will be used.
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reg dest_find_tready;
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always @(*) begin
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if (s_axis_chdr_hdr_valid) begin
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case (s_axis_chdr_tid)
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CHDR_MGMT_ROUTE_EPID:
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dest_find_tready = find_tready;
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CHDR_MGMT_ROUTE_TDEST:
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dest_find_tready = dest_i_tready;
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CHDR_MGMT_RETURN_TO_SRC:
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dest_find_tready = dest_i_tready;
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default:
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dest_find_tready = dest_i_tready; // We should never get here
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endcase
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end else begin
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dest_find_tready = 1'b1;
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end
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end
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// We can accept a transfer from the input CHDR stream only if the the packet
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// gate and dest/find datapaths are ready.
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assign s_axis_chdr_tready = s_axis_chdr_tvalid &&
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gate_i_tready &&
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dest_find_tready;
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// The chdr_header_stb signal indicates when we write data into the dest/find
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// data path. This happens when we're accepting the header word of the packet
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// into the packet gate.
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wire chdr_header_stb = s_axis_chdr_tvalid &&
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s_axis_chdr_tready &&
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s_axis_chdr_hdr_valid;
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// **************************************************************************
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// WARNING: The logic below violates AXI-Stream by having a tready -> tvalid
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// dependency To ensure no deadlocks, we must place FIFOs downstream
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// of gate_i_*, find_* and dest_i_*
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// Here we decide if we need to do a lookup using the find_* path or if the
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// destination is known and can be put directly on the dest_* path.
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//
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// Start a lookup request if the TID is CHDR_MGMT_ROUTE_EPID.
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assign find_tdata = chdr_get_dst_epid(s_axis_chdr_tdata[63:0]);
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assign find_tvalid = chdr_header_stb &&
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(s_axis_chdr_tid == CHDR_MGMT_ROUTE_EPID);
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// Set TDEST directly if TID is CHDR_MGMT_ROUTE_TDEST or
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// CHDR_MGMT_RETURN_TO_SRC.
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assign dest_i_tdata = (s_axis_chdr_tid == CHDR_MGMT_ROUTE_TDEST) ?
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s_axis_chdr_tdest : NODE_ID[DEST_W-1:0];
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assign dest_i_tkeep = 1'b1;
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assign dest_i_tvalid = chdr_header_stb &&
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(s_axis_chdr_tid != CHDR_MGMT_ROUTE_EPID);
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// Input logic for axi_packet_gate
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assign gate_i_tdata = s_axis_chdr_tdata;
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assign gate_i_tlast = s_axis_chdr_tlast;
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assign gate_i_tvalid = s_axis_chdr_tready && s_axis_chdr_tvalid;
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//
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// **************************************************************************
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//---------------------------------------------------------------------------
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// Output Logic
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//---------------------------------------------------------------------------
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//
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// The destination for the packet (TDEST) must be valid before we allow the
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// header of the packet to pass through. So the packet must be blocked until
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// the output of the dest_o_* is valid. TDEST and TKEEP must remain valid
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// until the end of the packet.
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//
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//---------------------------------------------------------------------------
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assign m_axis_chdr_tdata = gate_o_tdata;
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assign m_axis_chdr_tlast = gate_o_tlast;
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assign m_axis_chdr_tdest = dest_o_tdata;
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assign m_axis_chdr_tkeep = dest_o_tkeep;
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assign m_axis_chdr_tvalid = gate_o_tvalid && dest_o_tvalid;
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assign gate_o_tready = m_axis_chdr_tvalid && m_axis_chdr_tready;
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assign dest_o_tready = m_axis_chdr_tvalid && m_axis_chdr_tready && m_axis_chdr_tlast;
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endmodule
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