fpga: lib: rfnoc: Make RFNoC packet gates removable
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output to make their packet gates optional. They are included by default. Having the packet gate in chdr_xb_ingress_buff can reduce contention in the crossbar. Having the packet gate in chdr_stream_output can reduce the latency for non-data packets (e.g., stream status updates). Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
This commit is contained in:
@@ -17,6 +17,7 @@
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// Parameters:
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// Parameters:
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// - CHDR_W : Width of the CHDR bus in bits
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// - CHDR_W : Width of the CHDR bus in bits
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// - MTU : Log2 of the maximum number of lines in a packet
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// - MTU : Log2 of the maximum number of lines in a packet
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// - EN_PKT_GATE : Enable packet gate to make each packet contiguous
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//
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//
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// Signals:
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// Signals:
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// - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
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// - m_axis_chdr_* : Output CHDR stream (AXI-Stream)
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@@ -25,7 +26,8 @@
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module chdr_stream_output #(
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module chdr_stream_output #(
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parameter CHDR_W = 256,
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parameter CHDR_W = 256,
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parameter MTU = 10
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parameter MTU = 10,
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parameter EN_PKT_GATE = 1
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)(
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)(
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// Clock, reset and settings
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// Clock, reset and settings
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input wire clk,
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input wire clk,
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@@ -84,15 +86,31 @@ module chdr_stream_output #(
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reg chdr_out_tlast, chdr_out_tvalid;
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reg chdr_out_tlast, chdr_out_tvalid;
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wire chdr_out_tready;
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wire chdr_out_tready;
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if (EN_PKT_GATE) begin : gen_pkt_gate
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axi_packet_gate #(
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axi_packet_gate #(
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.WIDTH(CHDR_W), .SIZE(MTU), .USE_AS_BUFF(0)
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.WIDTH (CHDR_W),
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.SIZE (MTU ),
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.USE_AS_BUFF(0 )
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) chdr_pkt_gate_i (
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) chdr_pkt_gate_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.clk (clk ),
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.i_tdata(chdr_out_tdata), .i_tlast(chdr_out_tlast), .i_terror(1'b0),
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.reset (rst ),
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.i_tvalid(chdr_out_tvalid), .i_tready(chdr_out_tready),
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.clear (1'b0 ),
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.o_tdata(m_axis_chdr_tdata), .o_tlast(m_axis_chdr_tlast),
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.i_tdata (chdr_out_tdata ),
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.o_tvalid(m_axis_chdr_tvalid), .o_tready(m_axis_chdr_tready)
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.i_tlast (chdr_out_tlast ),
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.i_terror(1'b0 ),
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.i_tvalid(chdr_out_tvalid ),
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.i_tready(chdr_out_tready ),
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.o_tdata (m_axis_chdr_tdata ),
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.o_tlast (m_axis_chdr_tlast ),
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.o_tvalid(m_axis_chdr_tvalid),
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.o_tready(m_axis_chdr_tready)
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);
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);
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end else begin : gen_no_pkt_gate
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assign m_axis_chdr_tdata = chdr_out_tdata;
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assign m_axis_chdr_tlast = chdr_out_tlast;
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assign m_axis_chdr_tvalid = chdr_out_tvalid;
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assign chdr_out_tready = m_axis_chdr_tready;
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end
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// ---------------------------------------------------
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// ---------------------------------------------------
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// Flow Control State
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// Flow Control State
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@@ -18,13 +18,16 @@
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// MTU : Maximum transmission unit, in WIDTH-sized words, is 2**MTU
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// MTU : Maximum transmission unit, in WIDTH-sized words, is 2**MTU
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// DEST_W : Width of the destination routing information (TDEST)
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// DEST_W : Width of the destination routing information (TDEST)
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// NODE_ID : Numeric identifier for this port
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// NODE_ID : Numeric identifier for this port
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// EN_PKT_GATE : Enable packet gate to make each packet contiguous. This
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// reduces congestion in the crossbar.
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//
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//
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module chdr_xb_ingress_buff #(
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module chdr_xb_ingress_buff #(
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parameter WIDTH = 64,
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parameter WIDTH = 64,
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parameter MTU = 10,
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parameter MTU = 10,
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parameter DEST_W = 4,
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parameter DEST_W = 4,
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parameter [9:0] NODE_ID = 0
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parameter [9:0] NODE_ID = 0,
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parameter EN_PKT_GATE = 1
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) (
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) (
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input wire clk,
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input wire clk,
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input wire reset,
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input wire reset,
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@@ -69,6 +72,7 @@ module chdr_xb_ingress_buff #(
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// The axi_packet_gate queues up an entire packet before letting it go out.
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// The axi_packet_gate queues up an entire packet before letting it go out.
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// This reduces congestion in the crossbar for slowly-built packets.
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// This reduces congestion in the crossbar for slowly-built packets.
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if (EN_PKT_GATE) begin : gen_pkt_gate
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axi_packet_gate #(
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axi_packet_gate #(
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.WIDTH (WIDTH),
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.WIDTH (WIDTH),
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.SIZE (MTU)
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.SIZE (MTU)
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@@ -86,6 +90,23 @@ module chdr_xb_ingress_buff #(
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.o_tvalid (gate_o_tvalid),
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.o_tvalid (gate_o_tvalid),
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.o_tready (gate_o_tready)
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.o_tready (gate_o_tready)
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);
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);
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end else begin : gen_no_pkt_gate
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axi_fifo_flop2 #(
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.WIDTH(WIDTH+1)
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) axi_fifo_flop2_i (
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.clk (clk ),
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.reset (reset ),
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.clear (1'b0 ),
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.i_tdata ({gate_i_tlast, gate_i_tdata}),
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.i_tvalid(gate_i_tvalid ),
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.i_tready(gate_i_tready ),
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.o_tdata ({gate_o_tlast, gate_o_tdata}),
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.o_tvalid(gate_o_tvalid ),
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.o_tready(gate_o_tready ),
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.space ( ),
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.occupied( )
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);
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end
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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