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fpga: tools: Put SIM_SRCS at end of compile order

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VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.


Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent b5230b0256
commit d37cc533a7
1 changed files with 1 additions and 1 deletions
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tools/scripts/launch_vlint.sh
+1 -1
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@@ -78,8 +78,8 @@ VHD_ARGS_FILE=vcomarglist.txt
# Replace any directories with the sources they contain
SOURCES=
SOURCES+=$(replace_dirs_with_source $VLINT_INC_SRCS)
SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS)
SOURCES+=$(replace_dirs_with_source $VLINT_DESIGN_SRCS)
SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS)
# Separate the files by type and determine include directories to use
V_FILES=