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fpga: rfnoc: Fix DDC overflow issue

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Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.


Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
This commit is contained in:
Niels Garibaldi
2025-02-26 22:09:04 -06:00
committed by Wade Fife
parent 2535aa4f1b
commit cfa8afcf37
2 changed files with 201 additions and 18 deletions
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lib/rfnoc/ddc.v
+20 -7
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@@ -67,6 +67,7 @@ module ddc #(
wire phase_tvalid, phase_tready, phase_tlast;
wire dds_out_tlast;
wire dds_out_tvalid;
wire dds_out_tready;
wire [15:0] dds_input_fifo_space, dds_input_fifo_occupied;
wire [17:0] scale_factor;
@@ -271,17 +272,29 @@ module ddc #(
/* IQ output */
.m_axis_dout_tlast(dds_out_tlast),
.m_axis_dout_tvalid(dds_out_tvalid),
.m_axis_dout_tready(ddc_chain_tready),
.m_axis_dout_tready(dds_out_tready),
.m_axis_dout_tdata({dds_out_q_tdata, dds_out_i_tdata})
);
//48 = WIDTH*2
//chop off top byte because it's not actually used and we want to match expected gain/bit use found in freq shift
assign i_dds_clip = {dds_out_i_tdata[15:0],8'h00};
assign q_dds_clip = {dds_out_q_tdata[15:0],8'h00};
assign strobe_dds_clip = dds_out_tvalid & sample_out_tready;
assign last_cic_decimate_in = dds_out_tlast;
// Drop MSBs to match expected gain/bit use found in freq shift
axi_clip_complex #(
.WIDTH_IN (WIDTH),
.WIDTH_OUT (WIDTH-8),
.FIFOSIZE (0))
axi_clip_complex_post_dds (
.clk(clk),
.reset(reset | clear),
.i_tdata({dds_out_i_tdata, dds_out_q_tdata}),
.i_tlast(dds_out_tlast),
.i_tvalid(dds_out_tvalid),
.i_tready(dds_out_tready),
.o_tdata({i_dds_clip[WIDTH-1:8], q_dds_clip[WIDTH-1:8]}),
.o_tlast(last_cic_decimate_in),
.o_tvalid(strobe_dds_clip),
.o_tready(ddc_chain_tready));
assign i_dds_clip[7:0] = 8'h00;
assign q_dds_clip[7:0] = 8'h00;
/** CIC DECIMATE **/
cic_decimate #(.WIDTH(WIDTH), .N(4), .MAX_RATE(CIC_MAX_DECIM)) cic_decimate_i (