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fpga: x400: propagate pps_sync changes

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Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96
This commit is contained in:
Javier Valenzuela
2023-10-17 10:18:17 -05:00
committed by Wade Fife
parent 4d38451f2a
commit ccfb94c062
12 changed files with 398 additions and 136 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/doc/X410/X410_FPGA_left.htm
+1
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@@ -350,6 +350,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG');">PPS_CROSSING_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X410/X410_FPGA_right.htm
+167 -45
View File
@@ -6621,8 +6621,8 @@ Control registers for PPS generation.
<td> <td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p> <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that <p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
to disable the PPS for changes on the other values. Use a wait time of to disable the PPS for changes on the other values. Use a wait time of
at least 1 second before changing this value to ensure the values are at least 1 second before changing this value to ensure the values are
stable for the next PPS edge.</p> stable for the next PPS edge.</p>
@@ -6631,7 +6631,7 @@ Control registers for PPS generation.
</tr> </tr>
<tr valign="top"> <tr valign="top">
<td class="bits">30</td> <td class="bits">30..26</td>
<td> <td>
<p><span class="name">Reserved</span><span class="attr"> </span></p> <p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p> <p></p>
@@ -6639,28 +6639,6 @@ Control registers for PPS generation.
</td> </td>
</tr> </tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top"> <tr valign="top">
<td class="bits">25..0</td> <td class="bits">25..0</td>
<td> <td>
@@ -6669,7 +6647,7 @@ Control registers for PPS generation.
desired aligned edge to issue the PPS in radio clock domain. This desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1 delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). <br> second (period of PPS). <br>
The value written to the register has to be reduced by 4 due to The value written to the register has to be reduced by 5 due to
HDL implementation.</p> HDL implementation.</p>
</td> </td>
@@ -6937,6 +6915,150 @@ Build seed used for this compilation. Making this value readable
</div> </div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG"></a>
<h3 class="register">Offset 0x0030: PPS_CROSSING_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PPS_CROSSING_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control registers for PPS clock crossing to the radio clock domain.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..21</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">20..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
</table>
</div> </div>
<div class="register"> <div class="register">
@@ -24984,19 +25106,6 @@ FPGA version.<BR/>
</tr> </tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top"> <tr valign="top">
<td class='value'>0</td> <td class='value'>0</td>
@@ -25017,7 +25126,7 @@ FPGA version.<BR/>
<td class='l'>0x00000000</td> <td class='l'>0x00000000</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td> </td>
@@ -25025,12 +25134,25 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>0</td> <td class='value'>1</td>
<td class='l'>0x00000000</td> <td class='l'>0x00000001</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td> </td>
@@ -25064,9 +25186,9 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>587472913</td> <td class='value'>587801865</td>
<td class='l'>0x23042011</td> <td class='l'>0x23092509</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
top/x400/doc/X440/X440_FPGA_left.htm
+1
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@@ -377,6 +377,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG');">PPS_CROSSING_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p> <p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X440/X440_FPGA_right.htm
+167 -45
View File
@@ -6907,8 +6907,8 @@ Control registers for PPS generation.
<td> <td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p> <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that <p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
to disable the PPS for changes on the other values. Use a wait time of to disable the PPS for changes on the other values. Use a wait time of
at least 1 second before changing this value to ensure the values are at least 1 second before changing this value to ensure the values are
stable for the next PPS edge.</p> stable for the next PPS edge.</p>
@@ -6917,7 +6917,7 @@ Control registers for PPS generation.
</tr> </tr>
<tr valign="top"> <tr valign="top">
<td class="bits">30</td> <td class="bits">30..26</td>
<td> <td>
<p><span class="name">Reserved</span><span class="attr"> </span></p> <p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p> <p></p>
@@ -6925,28 +6925,6 @@ Control registers for PPS generation.
</td> </td>
</tr> </tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top"> <tr valign="top">
<td class="bits">25..0</td> <td class="bits">25..0</td>
<td> <td>
@@ -6955,7 +6933,7 @@ Control registers for PPS generation.
desired aligned edge to issue the PPS in radio clock domain. This desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1 delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). <br> second (period of PPS). <br>
The value written to the register has to be reduced by 4 due to The value written to the register has to be reduced by 5 due to
HDL implementation.</p> HDL implementation.</p>
</td> </td>
@@ -7223,6 +7201,150 @@ Build seed used for this compilation. Making this value readable
</div> </div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG"></a>
<h3 class="register">Offset 0x0030: PPS_CROSSING_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PPS_CROSSING_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control registers for PPS clock crossing to the radio clock domain.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..21</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">20..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
</table>
</div> </div>
<div class="register"> <div class="register">
@@ -28905,19 +29027,6 @@ FPGA version.<BR/>
</tr> </tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top"> <tr valign="top">
<td class='value'>0</td> <td class='value'>0</td>
@@ -28938,7 +29047,7 @@ FPGA version.<BR/>
<td class='l'>0x00000000</td> <td class='l'>0x00000000</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td> </td>
@@ -28946,12 +29055,25 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>0</td> <td class='value'>1</td>
<td class='l'>0x00000000</td> <td class='l'>0x00000001</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td> </td>
@@ -28985,9 +29107,9 @@ FPGA version.<BR/>
<tr valign="top"> <tr valign="top">
<td class='value'>587472913</td> <td class='value'>587801865</td>
<td class='l'>0x23042011</td> <td class='l'>0x23092509</td>
<td class="l" style="text-align: left;"> <td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
top/x400/regmap/global_regs_regmap_utils.vh
+13 -7
View File
@@ -22,6 +22,7 @@
// CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v) // CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v)
// CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v) // CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v)
// BUILD_SEED_REG : 0x28 (x4xx_global_regs.v) // BUILD_SEED_REG : 0x28 (x4xx_global_regs.v)
// PPS_CROSSING_REG : 0x30 (x4xx_global_regs.v)
// GPS_CTRL_REG : 0x38 (x4xx_global_regs.v) // GPS_CTRL_REG : 0x38 (x4xx_global_regs.v)
// GPS_STATUS_REG : 0x3C (x4xx_global_regs.v) // GPS_STATUS_REG : 0x3C (x4xx_global_regs.v)
// DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v) // DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v)
@@ -156,16 +157,10 @@
// PPS_CTRL_REG Register (from x4xx_global_regs.v) // PPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam PPS_CTRL_REG = 'h1C; // Register Offset localparam PPS_CTRL_REG = 'h1C; // Register Offset
localparam PPS_CTRL_REG_SIZE = 32; // register width in bits localparam PPS_CTRL_REG_SIZE = 32; // register width in bits
localparam PPS_CTRL_REG_MASK = 32'hBFFFFFFF; localparam PPS_CTRL_REG_MASK = 32'h83FFFFFF;
localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PRC_RC1_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 27; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 26; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC0_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
@@ -188,6 +183,17 @@
localparam BUILD_SEED_REG_SIZE = 32; // register width in bits localparam BUILD_SEED_REG_SIZE = 32; // register width in bits
localparam BUILD_SEED_REG_MASK = 32'h0; localparam BUILD_SEED_REG_MASK = 32'h0;
// PPS_CROSSING_REG Register (from x4xx_global_regs.v)
localparam PPS_CROSSING_REG = 'h30; // Register Offset
localparam PPS_CROSSING_REG_SIZE = 32; // register width in bits
localparam PPS_CROSSING_REG_MASK = 32'h1F001F;
localparam PRC_RC0_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 4; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 0; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC1_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 20; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 16; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
// GPS_CTRL_REG Register (from x4xx_global_regs.v) // GPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam GPS_CTRL_REG = 'h38; // Register Offset localparam GPS_CTRL_REG = 'h38; // Register Offset
localparam GPS_CTRL_REG_SIZE = 32; // register width in bits localparam GPS_CTRL_REG_SIZE = 32; // register width in bits
top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+3 -3
View File
@@ -79,13 +79,13 @@
// Enumerated type FPGA_VERSION // Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7; localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION // Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7; localparam RF_CORE_100M_VERSION_SIZE = 7;
top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+3 -3
View File
@@ -79,13 +79,13 @@
// Enumerated type FPGA_VERSION // Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7; localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_FULL_VERSION // Enumerated type RF_CORE_FULL_VERSION
localparam RF_CORE_FULL_VERSION_SIZE = 7; localparam RF_CORE_FULL_VERSION_SIZE = 7;
top/x400/x4xx.v
+6 -6
View File
@@ -494,7 +494,7 @@ module x4xx (
wire [ 7:0] pll_sync_delay; wire [ 7:0] pll_sync_delay;
wire [ 7:0] pps_brc_delay; wire [ 7:0] pps_brc_delay;
wire [25:0] pps_prc_delay; wire [25:0] pps_prc_delay;
wire [ 3:0] prc_rc_divider; wire [ 9:0] prc_rc_divider;
wire pps_rc_enabled; wire pps_rc_enabled;
x4xx_pps_sync x4xx_pps_sync_i ( x4xx_pps_sync x4xx_pps_sync_i (
@@ -3032,8 +3032,8 @@ module x4xx (
.pll_sync_done (pll_sync_done), .pll_sync_done (pll_sync_done),
.pps_brc_delay (pps_brc_delay), .pps_brc_delay (pps_brc_delay),
.pps_prc_delay (pps_prc_delay), .pps_prc_delay (pps_prc_delay),
.prc_rc0_divider (prc_rc_divider[1:0]), .prc_rc0_divider (prc_rc_divider[4:0]),
.prc_rc1_divider (prc_rc_divider[3:2]), .prc_rc1_divider (prc_rc_divider[9:5]),
.pps_rc_enabled (pps_rc_enabled), .pps_rc_enabled (pps_rc_enabled),
.rx_data (rx_data_iq), .rx_data (rx_data_iq),
.rx_stb (rx_stb), .rx_stb (rx_stb),
@@ -3194,12 +3194,12 @@ endmodule
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info> // </info>
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="8"/> // <value name="FPGA_CURRENT_VERSION_MAJOR" integer="8"/>
// <value name="FPGA_CURRENT_VERSION_MINOR" integer="0"/> // <value name="FPGA_CURRENT_VERSION_MINOR" integer="1"/>
// <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/> // <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="8"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="8"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="1"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x23042011"/> // <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x23092509"/>
// </enumeratedtype> // </enumeratedtype>
// </group> // </group>
//</regmap> //</regmap>
top/x400/x4xx_core.v
+2 -2
View File
@@ -128,8 +128,8 @@ module x4xx_core #(
input pll_sync_done, input pll_sync_done,
output [ 7:0] pps_brc_delay, output [ 7:0] pps_brc_delay,
output [25:0] pps_prc_delay, output [25:0] pps_prc_delay,
output [ 1:0] prc_rc0_divider, output [ 4:0] prc_rc0_divider,
output [ 1:0] prc_rc1_divider, output [ 4:0] prc_rc1_divider,
output pps_rc_enabled, output pps_rc_enabled,
// Radio Data // Radio Data
top/x400/x4xx_core_common.v
+2 -2
View File
@@ -79,8 +79,8 @@ module x4xx_core_common #(
input wire pll_sync_done, input wire pll_sync_done,
output wire [ 7:0] pps_brc_delay, output wire [ 7:0] pps_brc_delay,
output wire [25:0] pps_prc_delay, output wire [25:0] pps_prc_delay,
output wire [ 1:0] prc_rc0_divider, output wire [ 4:0] prc_rc0_divider,
output wire [ 1:0] prc_rc1_divider, output wire [ 4:0] prc_rc1_divider,
output wire pps_rc_enabled, output wire pps_rc_enabled,
// Timekeeper (Domain: radio_clk) // Timekeeper (Domain: radio_clk)
top/x400/x4xx_global_regs.v
+28 -19
View File
@@ -55,8 +55,8 @@ module x4xx_global_regs #(
input wire pll_sync_done, input wire pll_sync_done,
output reg [ 7:0] pps_brc_delay = 8'b0, output reg [ 7:0] pps_brc_delay = 8'b0,
output reg [25:0] pps_prc_delay = 26'b0, output reg [25:0] pps_prc_delay = 26'b0,
output reg [ 1:0] prc_rc0_divider = 2'b0, output reg [ 4:0] prc_rc0_divider = 5'b0,
output reg [ 1:0] prc_rc1_divider = 2'b0, output reg [ 4:0] prc_rc1_divider = 5'b0,
output reg pps_rc_enabled = 1'b0, output reg pps_rc_enabled = 1'b0,
// Misc control and status signals (domain: s_ctrlport_clk) // Misc control and status signals (domain: s_ctrlport_clk)
@@ -199,9 +199,12 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin REG_BASE + PPS_CTRL_REG: begin
pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY]; pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end
REG_BASE + PPS_CROSSING_REG: begin
prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER]; prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER];
prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER]; prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end end
REG_BASE + SERIAL_NUM_LOW_REG: begin REG_BASE + SERIAL_NUM_LOW_REG: begin
@@ -281,9 +284,12 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin REG_BASE + PPS_CTRL_REG: begin
s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled; s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end
REG_BASE + PPS_CROSSING_REG: begin
s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider; s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider;
s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider; s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end end
REG_BASE + CHDR_CLK_RATE_REG: begin REG_BASE + CHDR_CLK_RATE_REG: begin
@@ -582,21 +588,7 @@ endmodule
// desired aligned edge to issue the PPS in radio clock domain. This // desired aligned edge to issue the PPS in radio clock domain. This
// delay is configurable to any aligned edge within a maximum delay of 1 // delay is configurable to any aligned edge within a maximum delay of 1
// second (period of PPS). <br> // second (period of PPS). <br>
// The value written to the register has to be reduced by 4 due to // The value written to the register has to be reduced by 5 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC1_DIVIDER" range="27..26">
// <info>
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="29..28">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation. // HDL implementation.
// </info> // </info>
// </bitfield> // </bitfield>
@@ -629,6 +621,23 @@ endmodule
// register. // register.
// </info> // </info>
// </register> // </register>
// <register name="PPS_CROSSING_REG" offset="0x30" size="32">
// <info>Control registers for PPS clock crossing to the radio clock domain.</info>
// <bitfield name="PRC_RC1_DIVIDER" range="20..16">
// <info>
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to follow the following formula:
// <code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code>
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="4..0">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to follow the following formula:
// <code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code>
// </info>
// </bitfield>
// </register>
// <register name="QSFP_PORT_0_0_INFO_REG" offset="0x60" size="32" writable="false"> // <register name="QSFP_PORT_0_0_INFO_REG" offset="0x60" size="32" writable="false">
// <info> // <info>
// Returns information from the QSFP0 Lane0. // Returns information from the QSFP0 Lane0.
top/x400/x4xx_pps_sync.v
+5 -4
View File
@@ -357,9 +357,10 @@ module x4xx_pps_sync #(
.out (pps_prc_delay_prc) .out (pps_prc_delay_prc)
); );
reg [25:0] delay_counter_prc = 26'b0; reg [25:0] delay_counter_prc = 26'b0;
reg pps_delayed_prc = 1'b0; reg pps_delayed_prc = 1'b0;
reg pps_prc_delayed = 1'b0; reg pps_delayed_prc_out = 1'b0;
reg pps_prc_delayed = 1'b0;
always @(posedge pll_ref_clk) begin always @(posedge pll_ref_clk) begin
// Disable delayed rising edge by default // Disable delayed rising edge by default
pps_delayed_prc <= 1'b0; pps_delayed_prc <= 1'b0;
@@ -441,7 +442,7 @@ module x4xx_pps_sync #(
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
assign debug[0] = pps_delayed_brc; assign debug[0] = pps_delayed_brc;
assign debug[1] = pps_delayed_prc; assign debug[1] = pps_delayed_prc_out;
endmodule endmodule