From ccfb94c0621035764c8104b6d36d8807145bd597 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Fri, 22 Sep 2023 17:09:44 -0500 Subject: [PATCH] fpga: x400: propagate pps_sync changes Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96 --- top/x400/doc/X410/X410_FPGA_left.htm | 1 + top/x400/doc/X410/X410_FPGA_right.htm | 212 ++++++++++++++---- top/x400/doc/X440/X440_FPGA_left.htm | 1 + top/x400/doc/X440/X440_FPGA_right.htm | 212 ++++++++++++++---- top/x400/regmap/global_regs_regmap_utils.vh | 20 +- .../x410/versioning_regs_regmap_utils.vh | 6 +- .../x440/versioning_regs_regmap_utils.vh | 6 +- top/x400/x4xx.v | 12 +- top/x400/x4xx_core.v | 4 +- top/x400/x4xx_core_common.v | 4 +- top/x400/x4xx_global_regs.v | 47 ++-- top/x400/x4xx_pps_sync.v | 9 +- 12 files changed, 398 insertions(+), 136 deletions(-) diff --git a/top/x400/doc/X410/X410_FPGA_left.htm b/top/x400/doc/X410/X410_FPGA_left.htm index 869b9e5..b6dfa5b 100644 --- a/top/x400/doc/X410/X410_FPGA_left.htm +++ b/top/x400/doc/X410/X410_FPGA_left.htm @@ -350,6 +350,7 @@

CHDR_CLK_RATE_REG

CHDR_CLK_COUNT_REG

BUILD_SEED_REG

+

PPS_CROSSING_REG

GPS_CTRL_REG

GPS_STATUS_REG

DBOARD_CTRL_REG

diff --git a/top/x400/doc/X410/X410_FPGA_right.htm b/top/x400/doc/X410/X410_FPGA_right.htm index bbb4f5f..8f4be14 100644 --- a/top/x400/doc/X410/X410_FPGA_right.htm +++ b/top/x400/doc/X410/X410_FPGA_right.htm @@ -6621,8 +6621,8 @@ Control registers for PPS generation.

PPS_RC_ENABLED

Enables the PPS signal in radio clock domain. Please make sure that - the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and - PRC_RC1_DIVIDER are set before enabling this bit. It is recommended + the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and + PRC_RC1_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the next PPS edge.

@@ -6631,7 +6631,7 @@ Control registers for PPS generation. - 30 + 30..26

Reserved

@@ -6639,28 +6639,6 @@ Control registers for PPS generation. - - 29..28 - -

PRC_RC0_DIVIDER

-

Clock multiplier used to generate radio clock 0 from PLL reference clock. - The value written to the register has to be reduced by 2 due to - HDL implementation.

- - - - - - 27..26 - -

PRC_RC1_DIVIDER

-

Clock multiplier used to generate radio clock 1 from PLL reference clock. - The value written to the register has to be reduced by 2 due to - HDL implementation.

- - - - 25..0 @@ -6669,7 +6647,7 @@ Control registers for PPS generation. desired aligned edge to issue the PPS in radio clock domain. This delay is configurable to any aligned edge within a maximum delay of 1 second (period of PPS).
- The value written to the register has to be reduced by 4 due to + The value written to the register has to be reduced by 5 due to HDL implementation.

@@ -6937,6 +6915,150 @@ Build seed used for this compilation. Making this value readable + + +
+ + +

Offset 0x0030: PPS_CROSSING_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
PPS_CROSSING_REG
  offset=0x0030
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0030 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Control registers for PPS clock crossing to the radio clock domain. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..21 +

Reserved

+

+ +
20..16 +

PRC_RC1_DIVIDER

+

Clock multiplier used to generate radio clock 1 from PLL reference clock. + The value written to the register has to follow the following formula: + PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2

+ +
15..8 +

Reserved

+

+ +
7..5 +

Reserved

+

+ +
4..0 +

PRC_RC0_DIVIDER

+

Clock multiplier used to generate radio clock 0 from PLL reference clock. + The value written to the register has to follow the following formula: + PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2

+ +
+
@@ -24984,19 +25106,6 @@ FPGA version.
- - - 0 - - 0x00000000 - - -

FPGA_CURRENT_VERSION_MINOR

- - - - - 0 @@ -25017,7 +25126,7 @@ FPGA version.
0x00000000 -

FPGA_OLDEST_COMPATIBLE_VERSION_MINOR

+

FPGA_OLDEST_COMPATIBLE_VERSION_BUILD

@@ -25025,12 +25134,25 @@ FPGA version.
- 0 + 1 - 0x00000000 + 0x00000001 -

FPGA_OLDEST_COMPATIBLE_VERSION_BUILD

+

FPGA_CURRENT_VERSION_MINOR

+ + + + + + + + 1 + + 0x00000001 + + +

FPGA_OLDEST_COMPATIBLE_VERSION_MINOR

@@ -25064,9 +25186,9 @@ FPGA version.
- 587472913 + 587801865 - 0x23042011 + 0x23092509

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/top/x400/doc/X440/X440_FPGA_left.htm b/top/x400/doc/X440/X440_FPGA_left.htm index 9ac613b..06d5bba 100644 --- a/top/x400/doc/X440/X440_FPGA_left.htm +++ b/top/x400/doc/X440/X440_FPGA_left.htm @@ -377,6 +377,7 @@

CHDR_CLK_RATE_REG

CHDR_CLK_COUNT_REG

BUILD_SEED_REG

+

PPS_CROSSING_REG

GPS_CTRL_REG

GPS_STATUS_REG

DBOARD_CTRL_REG

diff --git a/top/x400/doc/X440/X440_FPGA_right.htm b/top/x400/doc/X440/X440_FPGA_right.htm index e9aa8c2..f95f386 100644 --- a/top/x400/doc/X440/X440_FPGA_right.htm +++ b/top/x400/doc/X440/X440_FPGA_right.htm @@ -6907,8 +6907,8 @@ Control registers for PPS generation.

PPS_RC_ENABLED

Enables the PPS signal in radio clock domain. Please make sure that - the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and - PRC_RC1_DIVIDER are set before enabling this bit. It is recommended + the values of PPS_BRC_DELAY, PPS_PRC_DELAY, PRC_RC0_DIVIDER and + PRC_RC1_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the next PPS edge.

@@ -6917,7 +6917,7 @@ Control registers for PPS generation. - 30 + 30..26

Reserved

@@ -6925,28 +6925,6 @@ Control registers for PPS generation. - - 29..28 - -

PRC_RC0_DIVIDER

-

Clock multiplier used to generate radio clock 0 from PLL reference clock. - The value written to the register has to be reduced by 2 due to - HDL implementation.

- - - - - - 27..26 - -

PRC_RC1_DIVIDER

-

Clock multiplier used to generate radio clock 1 from PLL reference clock. - The value written to the register has to be reduced by 2 due to - HDL implementation.

- - - - 25..0 @@ -6955,7 +6933,7 @@ Control registers for PPS generation. desired aligned edge to issue the PPS in radio clock domain. This delay is configurable to any aligned edge within a maximum delay of 1 second (period of PPS).
- The value written to the register has to be reduced by 4 due to + The value written to the register has to be reduced by 5 due to HDL implementation.

@@ -7223,6 +7201,150 @@ Build seed used for this compilation. Making this value readable
+ + +
+ + +

Offset 0x0030: PPS_CROSSING_REG Register (R|W)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
PPS_CROSSING_REG
  offset=0x0030
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0030 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Control registers for PPS clock crossing to the radio clock domain. + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsName
31..24 +

Reserved

+

+ +
23..21 +

Reserved

+

+ +
20..16 +

PRC_RC1_DIVIDER

+

Clock multiplier used to generate radio clock 1 from PLL reference clock. + The value written to the register has to follow the following formula: + PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2

+ +
15..8 +

Reserved

+

+ +
7..5 +

Reserved

+

+ +
4..0 +

PRC_RC0_DIVIDER

+

Clock multiplier used to generate radio clock 0 from PLL reference clock. + The value written to the register has to follow the following formula: + PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2

+ +
+
@@ -28905,19 +29027,6 @@ FPGA version.
- - - 0 - - 0x00000000 - - -

FPGA_CURRENT_VERSION_MINOR

- - - - - 0 @@ -28938,7 +29047,7 @@ FPGA version.
0x00000000 -

FPGA_OLDEST_COMPATIBLE_VERSION_MINOR

+

FPGA_OLDEST_COMPATIBLE_VERSION_BUILD

@@ -28946,12 +29055,25 @@ FPGA version.
- 0 + 1 - 0x00000000 + 0x00000001 -

FPGA_OLDEST_COMPATIBLE_VERSION_BUILD

+

FPGA_CURRENT_VERSION_MINOR

+ + + + + + + + 1 + + 0x00000001 + + +

FPGA_OLDEST_COMPATIBLE_VERSION_MINOR

@@ -28985,9 +29107,9 @@ FPGA version.
- 587472913 + 587801865 - 0x23042011 + 0x23092509

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/top/x400/regmap/global_regs_regmap_utils.vh b/top/x400/regmap/global_regs_regmap_utils.vh index 90618ca..04a1011 100644 --- a/top/x400/regmap/global_regs_regmap_utils.vh +++ b/top/x400/regmap/global_regs_regmap_utils.vh @@ -22,6 +22,7 @@ // CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v) // CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v) // BUILD_SEED_REG : 0x28 (x4xx_global_regs.v) + // PPS_CROSSING_REG : 0x30 (x4xx_global_regs.v) // GPS_CTRL_REG : 0x38 (x4xx_global_regs.v) // GPS_STATUS_REG : 0x3C (x4xx_global_regs.v) // DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v) @@ -156,16 +157,10 @@ // PPS_CTRL_REG Register (from x4xx_global_regs.v) localparam PPS_CTRL_REG = 'h1C; // Register Offset localparam PPS_CTRL_REG_SIZE = 32; // register width in bits - localparam PPS_CTRL_REG_MASK = 32'hBFFFFFFF; + localparam PPS_CTRL_REG_MASK = 32'h83FFFFFF; localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY - localparam PRC_RC1_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC1_DIVIDER - localparam PRC_RC1_DIVIDER_MSB = 27; //PPS_CTRL_REG:PRC_RC1_DIVIDER - localparam PRC_RC1_DIVIDER = 26; //PPS_CTRL_REG:PRC_RC1_DIVIDER - localparam PRC_RC0_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC0_DIVIDER - localparam PRC_RC0_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC0_DIVIDER - localparam PRC_RC0_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC0_DIVIDER localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED @@ -188,6 +183,17 @@ localparam BUILD_SEED_REG_SIZE = 32; // register width in bits localparam BUILD_SEED_REG_MASK = 32'h0; + // PPS_CROSSING_REG Register (from x4xx_global_regs.v) + localparam PPS_CROSSING_REG = 'h30; // Register Offset + localparam PPS_CROSSING_REG_SIZE = 32; // register width in bits + localparam PPS_CROSSING_REG_MASK = 32'h1F001F; + localparam PRC_RC0_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC0_DIVIDER + localparam PRC_RC0_DIVIDER_MSB = 4; //PPS_CROSSING_REG:PRC_RC0_DIVIDER + localparam PRC_RC0_DIVIDER = 0; //PPS_CROSSING_REG:PRC_RC0_DIVIDER + localparam PRC_RC1_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC1_DIVIDER + localparam PRC_RC1_DIVIDER_MSB = 20; //PPS_CROSSING_REG:PRC_RC1_DIVIDER + localparam PRC_RC1_DIVIDER = 16; //PPS_CROSSING_REG:PRC_RC1_DIVIDER + // GPS_CTRL_REG Register (from x4xx_global_regs.v) localparam GPS_CTRL_REG = 'h38; // Register Offset localparam GPS_CTRL_REG_SIZE = 32; // register width in bits diff --git a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh index 3f4374c..a61ebdf 100644 --- a/top/x400/regmap/x410/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/x410/versioning_regs_regmap_utils.vh @@ -79,13 +79,13 @@ // Enumerated type FPGA_VERSION localparam FPGA_VERSION_SIZE = 7; - localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD - localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD + localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh index 9d55b32..a92beca 100644 --- a/top/x400/regmap/x440/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh @@ -79,13 +79,13 @@ // Enumerated type FPGA_VERSION localparam FPGA_VERSION_SIZE = 7; - localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD - localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD + localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_FULL_VERSION localparam RF_CORE_FULL_VERSION_SIZE = 7; diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index f346d6f..5033faa 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -494,7 +494,7 @@ module x4xx ( wire [ 7:0] pll_sync_delay; wire [ 7:0] pps_brc_delay; wire [25:0] pps_prc_delay; - wire [ 3:0] prc_rc_divider; + wire [ 9:0] prc_rc_divider; wire pps_rc_enabled; x4xx_pps_sync x4xx_pps_sync_i ( @@ -3032,8 +3032,8 @@ module x4xx ( .pll_sync_done (pll_sync_done), .pps_brc_delay (pps_brc_delay), .pps_prc_delay (pps_prc_delay), - .prc_rc0_divider (prc_rc_divider[1:0]), - .prc_rc1_divider (prc_rc_divider[3:2]), + .prc_rc0_divider (prc_rc_divider[4:0]), + .prc_rc1_divider (prc_rc_divider[9:5]), .pps_rc_enabled (pps_rc_enabled), .rx_data (rx_data_iq), .rx_stb (rx_stb), @@ -3194,12 +3194,12 @@ endmodule //
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // // -// +// // // -// +// // -// +// // // // diff --git a/top/x400/x4xx_core.v b/top/x400/x4xx_core.v index 71fdd68..f92a1e9 100644 --- a/top/x400/x4xx_core.v +++ b/top/x400/x4xx_core.v @@ -128,8 +128,8 @@ module x4xx_core #( input pll_sync_done, output [ 7:0] pps_brc_delay, output [25:0] pps_prc_delay, - output [ 1:0] prc_rc0_divider, - output [ 1:0] prc_rc1_divider, + output [ 4:0] prc_rc0_divider, + output [ 4:0] prc_rc1_divider, output pps_rc_enabled, // Radio Data diff --git a/top/x400/x4xx_core_common.v b/top/x400/x4xx_core_common.v index 27eff80..4646c59 100644 --- a/top/x400/x4xx_core_common.v +++ b/top/x400/x4xx_core_common.v @@ -79,8 +79,8 @@ module x4xx_core_common #( input wire pll_sync_done, output wire [ 7:0] pps_brc_delay, output wire [25:0] pps_prc_delay, - output wire [ 1:0] prc_rc0_divider, - output wire [ 1:0] prc_rc1_divider, + output wire [ 4:0] prc_rc0_divider, + output wire [ 4:0] prc_rc1_divider, output wire pps_rc_enabled, // Timekeeper (Domain: radio_clk) diff --git a/top/x400/x4xx_global_regs.v b/top/x400/x4xx_global_regs.v index c4ca53d..80d1381 100644 --- a/top/x400/x4xx_global_regs.v +++ b/top/x400/x4xx_global_regs.v @@ -55,8 +55,8 @@ module x4xx_global_regs #( input wire pll_sync_done, output reg [ 7:0] pps_brc_delay = 8'b0, output reg [25:0] pps_prc_delay = 26'b0, - output reg [ 1:0] prc_rc0_divider = 2'b0, - output reg [ 1:0] prc_rc1_divider = 2'b0, + output reg [ 4:0] prc_rc0_divider = 5'b0, + output reg [ 4:0] prc_rc1_divider = 5'b0, output reg pps_rc_enabled = 1'b0, // Misc control and status signals (domain: s_ctrlport_clk) @@ -199,9 +199,12 @@ module x4xx_global_regs #( REG_BASE + PPS_CTRL_REG: begin pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY]; + pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED]; + end + + REG_BASE + PPS_CROSSING_REG: begin prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER]; prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER]; - pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED]; end REG_BASE + SERIAL_NUM_LOW_REG: begin @@ -281,9 +284,12 @@ module x4xx_global_regs #( REG_BASE + PPS_CTRL_REG: begin s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled; + s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay; + end + + REG_BASE + PPS_CROSSING_REG: begin s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider; s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider; - s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay; end REG_BASE + CHDR_CLK_RATE_REG: begin @@ -582,21 +588,7 @@ endmodule // desired aligned edge to issue the PPS in radio clock domain. This // delay is configurable to any aligned edge within a maximum delay of 1 // second (period of PPS).
    -// The value written to the register has to be reduced by 4 due to -// HDL implementation. -// -// -// -// -// Clock multiplier used to generate radio clock 1 from PLL reference clock. -// The value written to the register has to be reduced by 2 due to -// HDL implementation. -// -// -// -// -// Clock multiplier used to generate radio clock 0 from PLL reference clock. -// The value written to the register has to be reduced by 2 due to +// The value written to the register has to be reduced by 5 due to // HDL implementation. // // @@ -629,6 +621,23 @@ endmodule // register. // // +// +// Control registers for PPS clock crossing to the radio clock domain. +// +// +// Clock multiplier used to generate radio clock 1 from PLL reference clock. +// The value written to the register has to follow the following formula: +// PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2 +// +// +// +// +// Clock multiplier used to generate radio clock 0 from PLL reference clock. +// The value written to the register has to follow the following formula: +// PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2 +// +// +// // // // Returns information from the QSFP0 Lane0. diff --git a/top/x400/x4xx_pps_sync.v b/top/x400/x4xx_pps_sync.v index 53f7f0d..d8eba39 100644 --- a/top/x400/x4xx_pps_sync.v +++ b/top/x400/x4xx_pps_sync.v @@ -357,9 +357,10 @@ module x4xx_pps_sync #( .out (pps_prc_delay_prc) ); - reg [25:0] delay_counter_prc = 26'b0; - reg pps_delayed_prc = 1'b0; - reg pps_prc_delayed = 1'b0; + reg [25:0] delay_counter_prc = 26'b0; + reg pps_delayed_prc = 1'b0; + reg pps_delayed_prc_out = 1'b0; + reg pps_prc_delayed = 1'b0; always @(posedge pll_ref_clk) begin // Disable delayed rising edge by default pps_delayed_prc <= 1'b0; @@ -441,7 +442,7 @@ module x4xx_pps_sync #( //--------------------------------------------------------------------------- assign debug[0] = pps_delayed_brc; - assign debug[1] = pps_delayed_prc; + assign debug[1] = pps_delayed_prc_out; endmodule