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fpga: x400: propagate pps_sync changes

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Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96
This commit is contained in:
Javier Valenzuela
2023-10-17 10:18:17 -05:00
committed by Wade Fife
parent 4d38451f2a
commit ccfb94c062
12 changed files with 398 additions and 136 deletions
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top/x400/x4xx_global_regs.v
+28 -19
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@@ -55,8 +55,8 @@ module x4xx_global_regs #(
input wire pll_sync_done,
output reg [ 7:0] pps_brc_delay = 8'b0,
output reg [25:0] pps_prc_delay = 26'b0,
output reg [ 1:0] prc_rc0_divider = 2'b0,
output reg [ 1:0] prc_rc1_divider = 2'b0,
output reg [ 4:0] prc_rc0_divider = 5'b0,
output reg [ 4:0] prc_rc1_divider = 5'b0,
output reg pps_rc_enabled = 1'b0,
// Misc control and status signals (domain: s_ctrlport_clk)
@@ -199,9 +199,12 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end
REG_BASE + PPS_CROSSING_REG: begin
prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER];
prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end
REG_BASE + SERIAL_NUM_LOW_REG: begin
@@ -281,9 +284,12 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end
REG_BASE + PPS_CROSSING_REG: begin
s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider;
s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end
REG_BASE + CHDR_CLK_RATE_REG: begin
@@ -582,21 +588,7 @@ endmodule
// desired aligned edge to issue the PPS in radio clock domain. This
// delay is configurable to any aligned edge within a maximum delay of 1
// second (period of PPS). <br>
// The value written to the register has to be reduced by 4 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC1_DIVIDER" range="27..26">
// <info>
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="29..28">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// The value written to the register has to be reduced by 5 due to
// HDL implementation.
// </info>
// </bitfield>
@@ -629,6 +621,23 @@ endmodule
// register.
// </info>
// </register>
// <register name="PPS_CROSSING_REG" offset="0x30" size="32">
// <info>Control registers for PPS clock crossing to the radio clock domain.</info>
// <bitfield name="PRC_RC1_DIVIDER" range="20..16">
// <info>
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to follow the following formula:
// <code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code>
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="4..0">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to follow the following formula:
// <code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code>
// </info>
// </bitfield>
// </register>
// <register name="QSFP_PORT_0_0_INFO_REG" offset="0x60" size="32" writable="false">
// <info>
// Returns information from the QSFP0 Lane0.