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fpga: x400: propagate pps_sync changes

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Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96
This commit is contained in:
Javier Valenzuela
2023-10-17 10:18:17 -05:00
committed by Wade Fife
parent 4d38451f2a
commit ccfb94c062
12 changed files with 398 additions and 136 deletions
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top/x400/regmap/global_regs_regmap_utils.vh
+13 -7
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@@ -22,6 +22,7 @@
// CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v)
// CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v)
// BUILD_SEED_REG : 0x28 (x4xx_global_regs.v)
// PPS_CROSSING_REG : 0x30 (x4xx_global_regs.v)
// GPS_CTRL_REG : 0x38 (x4xx_global_regs.v)
// GPS_STATUS_REG : 0x3C (x4xx_global_regs.v)
// DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v)
@@ -156,16 +157,10 @@
// PPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam PPS_CTRL_REG = 'h1C; // Register Offset
localparam PPS_CTRL_REG_SIZE = 32; // register width in bits
localparam PPS_CTRL_REG_MASK = 32'hBFFFFFFF;
localparam PPS_CTRL_REG_MASK = 32'h83FFFFFF;
localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PRC_RC1_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 27; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 26; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC0_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
@@ -188,6 +183,17 @@
localparam BUILD_SEED_REG_SIZE = 32; // register width in bits
localparam BUILD_SEED_REG_MASK = 32'h0;
// PPS_CROSSING_REG Register (from x4xx_global_regs.v)
localparam PPS_CROSSING_REG = 'h30; // Register Offset
localparam PPS_CROSSING_REG_SIZE = 32; // register width in bits
localparam PPS_CROSSING_REG_MASK = 32'h1F001F;
localparam PRC_RC0_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 4; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 0; //PPS_CROSSING_REG:PRC_RC0_DIVIDER
localparam PRC_RC1_DIVIDER_SIZE = 5; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 20; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 16; //PPS_CROSSING_REG:PRC_RC1_DIVIDER
// GPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam GPS_CTRL_REG = 'h38; // Register Offset
localparam GPS_CTRL_REG_SIZE = 32; // register width in bits
top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+3 -3
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@@ -79,13 +79,13 @@
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+3 -3
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@@ -79,13 +79,13 @@
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h1; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23092509; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_FULL_VERSION
localparam RF_CORE_FULL_VERSION_SIZE = 7;