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fpga: x400: propagate pps_sync changes

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Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96
This commit is contained in:
Javier Valenzuela
2023-10-17 10:18:17 -05:00
committed by Wade Fife
parent 4d38451f2a
commit ccfb94c062
12 changed files with 398 additions and 136 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/doc/X410/X410_FPGA_left.htm
+1
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@@ -350,6 +350,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG');">PPS_CROSSING_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X410/X410_FPGA_right.htm
+167 -45
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@@ -6621,8 +6621,8 @@ Control registers for PPS generation.
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
to disable the PPS for changes on the other values. Use a wait time of
at least 1 second before changing this value to ensure the values are
stable for the next PPS edge.</p>
@@ -6631,7 +6631,7 @@ Control registers for PPS generation.
</tr>
<tr valign="top">
<td class="bits">30</td>
<td class="bits">30..26</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
@@ -6639,28 +6639,6 @@ Control registers for PPS generation.
</td>
</tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..0</td>
<td>
@@ -6669,7 +6647,7 @@ Control registers for PPS generation.
desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). <br>
The value written to the register has to be reduced by 4 due to
The value written to the register has to be reduced by 5 due to
HDL implementation.</p>
</td>
@@ -6937,6 +6915,150 @@ Build seed used for this compilation. Making this value readable
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG"></a>
<h3 class="register">Offset 0x0030: PPS_CROSSING_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X410_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PPS_CROSSING_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control registers for PPS clock crossing to the radio clock domain.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..21</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">20..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
</table>
</div>
<div class="register">
@@ -24984,19 +25106,6 @@ FPGA version.<BR/>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
@@ -25017,7 +25126,7 @@ FPGA version.<BR/>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
@@ -25025,12 +25134,25 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>0</td>
<td class='value'>1</td>
<td class='l'>0x00000000</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
@@ -25064,9 +25186,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>587472913</td>
<td class='value'>587801865</td>
<td class='l'>0x23042011</td>
<td class='l'>0x23092509</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
top/x400/doc/X440/X440_FPGA_left.htm
+1
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@@ -377,6 +377,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG');">PPS_CROSSING_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X440/X440_FPGA_right.htm
+167 -45
View File
@@ -6907,8 +6907,8 @@ Control registers for PPS generation.
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
<a href="#GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
to disable the PPS for changes on the other values. Use a wait time of
at least 1 second before changing this value to ensure the values are
stable for the next PPS edge.</p>
@@ -6917,7 +6917,7 @@ Control registers for PPS generation.
</tr>
<tr valign="top">
<td class="bits">30</td>
<td class="bits">30..26</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
@@ -6925,28 +6925,6 @@ Control registers for PPS generation.
</td>
</tr>
<tr valign="top">
<td class="bits">29..28</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">27..26</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to be reduced by 2 due to
HDL implementation.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..0</td>
<td>
@@ -6955,7 +6933,7 @@ Control registers for PPS generation.
desired aligned edge to issue the PPS in radio clock domain. This
delay is configurable to any aligned edge within a maximum delay of 1
second (period of PPS). <br>
The value written to the register has to be reduced by 4 due to
The value written to the register has to be reduced by 5 due to
HDL implementation.</p>
</td>
@@ -7223,6 +7201,150 @@ Build seed used for this compilation. Making this value readable
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG"></a>
<h3 class="register">Offset 0x0030: PPS_CROSSING_REG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|PPS_CROSSING_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X440_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">PPS_CROSSING_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0030</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0030
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Control registers for PPS clock crossing to the radio clock domain.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..21</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">20..16</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC1_DIVIDER"></a>PRC_RC1_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 1 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC1_DIVIDER = (RADIO_CLK_1 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..8</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">7..5</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CROSSING_REG|PRC_RC0_DIVIDER"></a>PRC_RC0_DIVIDER</span><span class="attr"> </span></p>
<p>Clock multiplier used to generate radio clock 0 from PLL reference clock.
The value written to the register has to follow the following formula:
<code>PRC_RC0_DIVIDER = (RADIO_CLK_0 / PRC_CLK) * 2 - 2</code></p>
</td>
</tr>
</table>
</div>
<div class="register">
@@ -28905,19 +29027,6 @@ FPGA version.<BR/>
</tr>
<tr valign="top">
<td class='value'>0</td>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>0</td>
@@ -28938,7 +29047,7 @@ FPGA version.<BR/>
<td class='l'>0x00000000</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
</td>
@@ -28946,12 +29055,25 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>0</td>
<td class='value'>1</td>
<td class='l'>0x00000000</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_BUILD'></a>FPGA_OLDEST_COMPATIBLE_VERSION_BUILD</p>
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
</tr>
<tr valign="top">
<td class='value'>1</td>
<td class='l'>0x00000001</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MINOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MINOR</p>
</td>
@@ -28985,9 +29107,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>587472913</td>
<td class='value'>587801865</td>
<td class='l'>0x23042011</td>
<td class='l'>0x23092509</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>