Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.

Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db

top/python/bit_to_zynq_bin.py

@@ -0,0 +1,62 @@
+#!/usr/bin/python
+import sys
+import os
+import struct
+
+def flip32(data):
+	sl = struct.Struct('<I')
+	sb = struct.Struct('>I')
+	b = buffer(data)
+	d = bytearray(len(data))
+	for offset in xrange(0, len(data), 4):
+		 sb.pack_into(d, offset, sl.unpack_from(b, offset)[0])
+	return d
+
+import argparse
+parser = argparse.ArgumentParser(description='Convert FPGA bit files to raw bin format suitable for flashing')
+parser.add_argument('-f', '--flip', dest='flip', action='store_true', default=False, help='Flip 32-bit endianess (needed for Zynq)')
+parser.add_argument("bitfile", help="Input bit file name")
+parser.add_argument("binfile", help="Output bin file name")
+args = parser.parse_args()
+
+short = struct.Struct('>H')
+ulong = struct.Struct('>I')
+
+bitfile = open(args.bitfile, 'rb')
+
+l = short.unpack(bitfile.read(2))[0]
+if l != 9:
+	raise Exception, "Missing <0009> header (0x%x), not a bit file" % l
+bitfile.read(l)
+l = short.unpack(bitfile.read(2))[0]
+d = bitfile.read(l)
+if d != 'a':
+	raise Exception, "Missing <a> header, not a bit file"
+
+l = short.unpack(bitfile.read(2))[0]
+d = bitfile.read(l)
+print "Design name:", d
+
+KEYNAMES = {'b': "Partname", 'c': "Date", 'd': "Time"}
+
+while 1:
+	k = bitfile.read(1)
+	if not k:
+		raise Exception, "unexpected EOF"
+	elif k == 'e':
+		l = ulong.unpack(bitfile.read(4))[0]
+		print "found binary data:", l
+		d = bitfile.read(l)
+		if args.flip:
+			d = flip32(d)
+		open(args.binfile, 'wb').write(d)
+		break
+	elif k in KEYNAMES:
+		l = short.unpack(bitfile.read(2))[0]
+		d = bitfile.read(l)
+		print KEYNAMES[k], d
+	else:
+		print "Unexpected key: ", k
+		l = short.unpack(bitfile.read(2))[0]
+		d = bitfile.read(l)
+

top/python/check_inout.py

@@ -0,0 +1,51 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+
+# Description:
+# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
+# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
+
+import sys
+import re
+
+if __name__=='__main__':
+  if len(sys.argv) == 2:
+    print "Usage: %s <top level Verilog file> <pin definition UCF>"
+    sys.exit(-1)
+
+  verilog_filename = sys.argv[1]
+  ucf_filename = sys.argv[2]
+
+  verilog_file = open(verilog_filename, 'r')
+  ucf_file = open(ucf_filename, 'r')
+
+  verilog_iolist = list()
+  ucf_iolist = list()
+
+  #read in all input, inout, and output declarations and compile a list
+  for line in verilog_file:
+    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
+      verilog_iolist.append(match)
+
+  for line in ucf_file:
+      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
+      if m is not None:
+        ucf_iolist.append(m.group(1))
+
+  #now find corresponding matches and error when you don't find one
+  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
+  err = False
+
+  for item in verilog_iolist:
+    if item not in ucf_iolist:
+      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+      err = True
+
+  if err:
+    sys.exit(-1)
+
+  print "No errors found."
+  sys.exit(0)

top/python/check_timing.py

@@ -0,0 +1,25 @@
+#!/usr/bin/env python
+#
+# Copyright 2011-2012 Ettus Research LLC
+#
+
+import sys
+import re
+
+def print_timing_constraint_summary(twr_file):
+    output = ""
+    keep = False
+    done = False
+    try: open(twr_file)
+    except IOError:
+        print "cannot open or find %s; no timing summary to print!"%twr_file
+        exit(-1)
+    for line in open(twr_file).readlines():
+        if 'Derived Constraint Report' in line: keep = True
+        if 'constraint' in line and 'met' in line: done = True
+        if not keep and done: keep = True
+        if keep: output += line
+        if done: break
+    print("\n\n"+output)
+
+if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])

top/python/make_lvbitx.py

@@ -0,0 +1,57 @@
+#!/usr/bin/env python
+#
+# Copyright 2012 Ettus Research LLC
+#
+
+
+import xml.etree.ElementTree as et
+import base64
+from optparse import OptionParser
+
+
+def main():
+    parser = OptionParser()
+    parser.add_option("-l", "--lvbitxfile", dest="lvbitxfile",
+                  help="donor labview fpga bitfile", metavar="LVBITXFILE")
+
+    parser.add_option("-b", "--bitfile", dest="bitfile",
+                  help="xilinx generated bitfile", metavar="BITFILE")
+
+    parser.add_option("-o", "--output", dest="outfile",
+                  help="output labview fpga bitfile", metavar="OUTFILE")
+
+    parser.add_option("-s", "--signature", dest="signature",
+                  help="output labview fpga bitfile signature", metavar="SIGNATURE",
+                  default="ABCDEFG")
+
+
+    (options, args) = parser.parse_args()
+
+    tree = et.parse(options.lvbitxfile)
+    root = tree.getroot()
+    bs = root.find('Bitstream')
+    if bs is None: return
+
+    print('Found "%s" tag in "%s"...' % (bs.tag, options.lvbitxfile))
+
+    print('Writing old bitfile content to "%s"...' % (options.bitfile+'.bak'))
+    f_old = open(options.bitfile+'.bak', 'w')
+    f_old.write(base64.b64decode(bs.text))
+    f_old.close()
+
+
+    print('Reading new bitfile "%s"...' % options.bitfile)
+    f = open(options.bitfile, 'r')
+    newbs = base64.b64encode(f.read())
+    f.close()
+
+
+    bs.text = newbs
+    print('Saving new labview bitfile to  "%s"...' % options.outfile)
+    tree.write(options.outfile, xml_declaration=True, encoding='utf-8')
+
+if __name__ == '__main__':
+    try:
+        main()
+    except KeyboardInterrupt:
+        pass