Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.

Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db

top/b200/coregen/chipscope_ila_256.v

@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2013 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.4
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila_256.v
+// /___/   /\     Timestamp  : Fri Mar 08 16:13:02 PST 2013
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila_256(
+    CONTROL,
+    CLK,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [255 : 0] TRIG0;
+
+endmodule