Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
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// vrlp_eth_framer
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// Takes a vrlp stream in and adds udp, ip, and ethernet framing
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// Uses 8 setting reg addresses. First 4 are simple registers:
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// BASE+0 : Upper 16 bits of ethernet src mac
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// BASE+1 : Lower 32 bits of ethernet src mac
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// BASE+2 : IP src address
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// BASE+3 : UDP src port
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//
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// Next 4 control write ports on a RAM indexed by destination field of stream ID
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// BASE+4 : Dest SID for next 3 regs
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// BASE+5 : Dest IP
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// BASE+6 : Dest UDP port, upper 16 bits of dest mac
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// BASE+7 : Lower 32 bits of dest mac
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//
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// in_tuser holds streamid
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module vrlp_eth_framer
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#(parameter BASE=0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [63:0] in_tdata, input [15:0] in_tuser, input in_tlast, input in_tvalid, output in_tready,
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output [63:0] out_tdata, output [3:0] out_tuser, output out_tlast, output out_tvalid, input out_tready,
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output [31:0] debug );
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localparam SR_AWIDTH = 8;
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reg [15:0] sid;
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reg [15:0] vrlp_len;
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reg [2:0] vef_state;
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localparam VEF_IDLE = 3'd0;
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localparam VEF_PAYLOAD = 3'd7;
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reg [63:0] tdata;
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always @(posedge clk)
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if(reset | clear)
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begin
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vef_state <= VEF_IDLE;
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sid <= 16'd0;
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vrlp_len <= 16'd0;
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end
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else
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case(vef_state)
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VEF_IDLE :
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if(in_tvalid)
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begin
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vef_state <= 1;
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sid <= in_tuser[15:0];
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vrlp_len <= in_tdata[15:0]; // modified for VRLP header
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end
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VEF_PAYLOAD :
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if(in_tvalid & out_tready)
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if(in_tlast)
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vef_state <= VEF_IDLE;
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default :
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if(out_tready)
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vef_state <= vef_state + 3'd1;
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endcase // case (vef_state)
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wire [15:0] vrlp_len_in_bytes = {vrlp_len[13:0],2'b00}; // Vrlp length is in 32-bit words
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assign in_tready = (vef_state == VEF_PAYLOAD) ? out_tready : 1'b0;
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assign out_tvalid = (vef_state == VEF_PAYLOAD) ? in_tvalid : (vef_state == VEF_IDLE) ? 1'b0 : 1'b1;
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assign out_tlast = (vef_state == VEF_PAYLOAD) ? in_tlast : 1'b0;
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assign out_tuser = ((vef_state == VEF_PAYLOAD) & in_tlast) ? {1'b0,vrlp_len_in_bytes[2:0]} : 4'b0000;
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assign out_tdata = tdata;
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wire [47:0] pad = 48'h0;
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wire [47:0] mac_src, mac_dst;
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wire [15:0] eth_type = 16'h0800;
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wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
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wire [15:0] ip_len = (16'd28 + vrlp_len_in_bytes); // 20 for IP, 8 for UDP
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wire [15:0] ident = 16'h0;
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wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
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wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
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wire [15:0] iphdr_checksum;
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wire [31:0] ip_src, ip_dst;
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wire [15:0] udp_src, udp_dst;
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wire [15:0] udp_len = (16'd8 + vrlp_len_in_bytes);
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wire [15:0] udp_checksum = 16'h0;
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setting_reg #(.my_addr(BASE), .awidth(SR_AWIDTH), .width(16)) set_mac_upper
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(.clk(clk), .rst(reset),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(mac_src[47:32]), .changed());
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setting_reg #(.my_addr(BASE+1), .awidth(SR_AWIDTH), .width(32)) set_mac_lower
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(.clk(clk), .rst(reset),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(mac_src[31:0]), .changed());
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setting_reg #(.my_addr(BASE+2), .awidth(SR_AWIDTH), .width(32)) set_ip
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(.clk(clk), .rst(reset),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(ip_src), .changed());
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setting_reg #(.my_addr(BASE+3), .awidth(SR_AWIDTH), .width(16)) set_udp
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(.clk(clk), .rst(reset),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(udp_src), .changed());
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// Tables of MAC/IP/UDP addresses
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wire [8:0] ram_addr; // FIXME we could skip this part if we had wider SR addresses
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setting_reg #(.my_addr(BASE+4), .awidth(SR_AWIDTH), .width(9)) set_ram_addr
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(.clk(clk), .rst(reset),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(ram_addr), .changed());
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ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_ip
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(.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+5)), .addra(ram_addr), .dia(set_data), .doa(),
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.clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(ip_dst));
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ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_udpmac
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(.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+6)), .addra(ram_addr), .dia(set_data), .doa(),
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.clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob({udp_dst,mac_dst[47:32]}));
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ram_2port #(.DWIDTH(32), .AWIDTH(9)) ram_maclower
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(.clka(clk), .ena(1'b1), .wea(set_stb & (set_addr == BASE+7)), .addra(ram_addr), .dia(set_data), .doa(),
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.clkb(clk), .enb(1'b1), .web(1'b0), .addrb(sid[8:0]), .dib(32'hFFFF_FFFF), .dob(mac_dst[31:0]));
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ip_hdr_checksum ip_hdr_checksum
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(.clk(clk), .in({misc_ip,ip_len,ident,flag_frag,ttl_prot,16'd0,ip_src,ip_dst}),
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.out(iphdr_checksum));
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always @*
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case(vef_state)
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1 : tdata <= { pad[47:0], mac_dst[47:32]};
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2 : tdata <= { mac_dst[31:0], mac_src[47:16]};
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3 : tdata <= { mac_src[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0] };
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4 : tdata <= { ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]};
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5 : tdata <= { ip_src, ip_dst};
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6 : tdata <= { udp_src, udp_dst, udp_len, udp_checksum};
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default : tdata <= in_tdata;
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endcase // case (vef_state)
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endmodule // vrlp_eth_framer
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