Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
@@ -0,0 +1,573 @@
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// Ethernet dispatcher
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// Incoming ethernet packets are examined and sent to the correct destination
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// There are 3 destinations, ZPU, other ethernet port (out), and vita router
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// Packets going to the vita router will have the ethernet/ip/udp headers stripped off.
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//
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// To make things simpler, we start out by sending all packets to zpu and out port.
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// By the end of the eth/ip/udp headers, we can determine where the correct destination is.
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// If the correct destination is vita, we send an error indication on the zpu and out ports,
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// which will cause the axi_packet_gate to drop those packets, and send the vita frame to
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// the vita port.
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//
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// If at the end of the headers we determine the packet should go to zpu, then we send an
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// error indication on the out port, the rest of the packet to zpu and nothing on vita.
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// If it should go to out, we send the error indication to zpu, the rest of the packet to out,
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// and nothing on vita.
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//
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// Downstream we should have adequate fifo space, otherwise we could get backed up here.
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//
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// No tuser bits sent to vita, as vita assumes there are no errors and that occupancy is
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// indicated by the length field of the vita header.
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//
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// Rules for forwarding:
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//
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// Ethernet Broadcast (Dst MAC = ff:ff:ff:ff:ff:ff). Forward to both ZPU and XO MAC.
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// ? Ethernet Multicast (Dst MAC = USRP_NEXT_HOP). Forward only to ZPU.
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// ? Ethernet Multicast (Dst MAC = Unknown). Forward only to XO.
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// Ethernet Unicast (Dst MAC = Unknown). Forward only to XO.
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// Ethernet Unicast (Dst MAC = local). Look deeper......
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// IP Broadcast. Forward to both ZPU and XO MAC. (Should be coverd by Eth broadcast)
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// IP Multicast. ? Unknow Action.
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// IP Unicast (Dst IP = local). Look deeper....
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// UDP (Port = Listed) and its a VRLP packet. Forward only to VITA Radio Core.
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// UDP (Port = Unknown). Forward only to ZPU.
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//
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//
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module eth_dispatch
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#(parameter BASE=0)
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(
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// Clocking and reset interface
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input clk,
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input reset,
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input clear,
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// Setting register interface
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input set_stb,
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input [15:0] set_addr,
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input [31:0] set_data,
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// Input 68bit AXI-Stream interface (from MAC)
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input [63:0] in_tdata,
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input [3:0] in_tuser,
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input in_tlast,
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input in_tvalid,
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output in_tready,
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// Output AXI-STream interface to VITA Radio Core
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output [63:0] vita_tdata,
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output [3:0] vita_tuser,
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output vita_tlast,
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output vita_tvalid,
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input vita_tready,
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// Output AXI-Stream interface to ZPU
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output [63:0] zpu_tdata,
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output [3:0] zpu_tuser,
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output zpu_tlast,
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output zpu_tvalid,
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input zpu_tready,
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// Output AXI-Stream interface to cross-over MAC
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output [63:0] xo_tdata,
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output [3:0] xo_tuser,
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output xo_tlast,
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output xo_tvalid,
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input xo_tready,
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// Debug
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output [31:0] debug
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);
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//
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// State machine declarations
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//
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reg [2:0] state;
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localparam WAIT_PACKET = 0;
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localparam READ_HEADER = 1;
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localparam FORWARD_ZPU = 2;
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localparam FORWARD_ZPU_AND_XO = 3;
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localparam FORWARD_XO = 4;
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localparam FORWARD_RADIO_CORE = 5;
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localparam DROP_PACKET = 6;
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localparam CLASSIFY_PACKET = 7;
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//
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// Small RAM stores packet header during parsing.
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//
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localparam HEADER_RAM_SIZE = 9;
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(*ram_style="distributed"*)
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reg [68:0] header_ram [HEADER_RAM_SIZE-1:0];
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reg [3:0] header_ram_addr;
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reg drop_this_packet;
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wire header_done = (header_ram_addr == HEADER_RAM_SIZE-1);
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reg fwd_input;
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//
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reg [63:0] in_tdata_reg;
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//
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wire out_tvalid;
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wire out_tready;
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wire out_tlast;
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wire [3:0] out_tuser;
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wire [63:0] out_tdata;
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//
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// Output AXI-STream interface to VITA Radio Core
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wire [63:0] vita_pre_tdata;
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wire [3:0] vita_pre_tuser;
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wire vita_pre_tlast;
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wire vita_pre_tvalid;
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wire vita_pre_tready;
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// Output AXI-Stream interface to ZPU
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wire [63:0] zpu_pre_tdata;
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wire [3:0] zpu_pre_tuser;
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wire zpu_pre_tlast;
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wire zpu_pre_tvalid;
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wire zpu_pre_tready;
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// Output AXI-Stream interface to cross-over MAC
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wire [63:0] xo_pre_tdata;
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wire [3:0] xo_pre_tuser;
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wire xo_pre_tlast;
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wire xo_pre_tvalid;
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wire xo_pre_tready;
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//
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// Packet Parse Flags
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//
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reg is_eth_dst_addr;
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reg is_eth_broadcast;
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reg is_eth_type_ipv4;
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reg is_ipv4_dst_addr;
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reg is_ipv4_proto_udp;
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reg is_ipv4_proto_icmp;
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reg [1:0] is_udp_dst_ports;
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reg is_icmp_no_fwd;
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reg is_chdr;
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//
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// Settings regs
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//
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wire [47:0] my_mac;
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setting_reg #(.my_addr(BASE), .awidth(16), .width(32)) sr_my_mac_lsb
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_mac[31:0]),.changed());
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setting_reg #(.my_addr(BASE+1), .awidth(16), .width(16)) sr_my_mac_msb
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_mac[47:32]),.changed());
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wire [31:0] my_ip;
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setting_reg #(.my_addr(BASE+2), .awidth(16), .width(32)) sr_my_ip
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_ip[31:0]),.changed());
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wire [15:0] my_port0, my_port1;
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setting_reg #(.my_addr(BASE+3), .awidth(16), .width(32)) sr_udp_port
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({my_port1[15:0],my_port0[15:0]}),.changed());
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wire forward_ndest, forward_bcast;
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setting_reg #(.my_addr(BASE+4), .awidth(16), .width(2)) sr_forward_ctrl
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({forward_ndest, forward_bcast}),.changed());
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wire [7:0] my_icmp_type, my_icmp_code;
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setting_reg #(.my_addr(BASE+5), .awidth(16), .width(16)) sr_icmp_ctrl
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({my_icmp_type, my_icmp_code}),.changed());
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assign debug =
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{
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1'b0, state, //4
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1'b0, in_tvalid, in_tready, in_tlast, //4
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1'b0, is_eth_dst_addr, is_eth_broadcast, is_eth_type_ipv4,
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is_ipv4_dst_addr, is_ipv4_proto_udp, is_udp_dst_ports, //8
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header_ram_addr[3:0], //4
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4'b0, 8'b0
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};
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//
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// Packet Forwarding State machine.
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//
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always @(posedge clk)
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if (reset || clear) begin
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state <= WAIT_PACKET;
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header_ram_addr <= 0;
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drop_this_packet <= 0;
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fwd_input <= 0;
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end else begin
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// Defaults.
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drop_this_packet <= 0;
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case(state)
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//
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// Wait for start of a packet
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// IJB: Add protection for a premature EOF here
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//
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WAIT_PACKET: begin
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if (in_tvalid && in_tready) begin
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header_ram[header_ram_addr] <= {in_tlast,in_tuser,in_tdata};
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header_ram_addr <= header_ram_addr + 1;
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state <= READ_HEADER;
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end
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fwd_input <= 0;
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end
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//
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// Continue to read full packet header into RAM.
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//
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READ_HEADER: begin
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if (in_tvalid && in_tready) begin
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header_ram[header_ram_addr] <= {in_tlast,in_tuser,in_tdata};
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// Have we reached end of fields we parse in header or got a short packet?
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if (header_done || in_tlast) begin
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// Make decision about where this packet is forwarded to.
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state <= CLASSIFY_PACKET;
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end // if (header_done || in_tlast)
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else begin
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header_ram_addr <= header_ram_addr + 1;
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state <= READ_HEADER;
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end // else: !if(header_done || in_tlast)
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end // if (in_tvalid && in_tready)
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end // case: READ_HEADER
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//
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// Classify Packet
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//
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CLASSIFY_PACKET: begin
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// Make decision about where this packet is forwarded to.
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if (is_eth_type_ipv4 && is_ipv4_proto_icmp && is_icmp_no_fwd) begin
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header_ram_addr <= 0;
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state <= FORWARD_ZPU;
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end else if (is_eth_broadcast) begin
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header_ram_addr <= 0;
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state <= forward_bcast? FORWARD_ZPU_AND_XO : FORWARD_ZPU;
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end else if (!is_eth_dst_addr) begin
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header_ram_addr <= 0;
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state <= forward_ndest? FORWARD_XO : DROP_PACKET;
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end else if ((is_udp_dst_ports != 0) && is_chdr) begin
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header_ram_addr <= 6; // Jump to CHDR
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state <= FORWARD_RADIO_CORE;
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end else if (drop_this_packet) begin
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header_ram_addr <= HEADER_RAM_SIZE-1;
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state <= DROP_PACKET;
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end else begin
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header_ram_addr <= 0;
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state <= FORWARD_ZPU;
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end
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end // case: CLASSIFY_PACKET
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//
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// Forward this packet only to local ZPU
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//
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FORWARD_ZPU: begin
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if (out_tvalid && out_tready) begin
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if (out_tlast) begin
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state <= WAIT_PACKET;
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end
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if (header_done) fwd_input <= 1;
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header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
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end
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end
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//
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// Forward this packet to both local ZPU and XO
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//
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FORWARD_ZPU_AND_XO: begin
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if (out_tvalid && out_tready) begin
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if (out_tlast) begin
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state <= WAIT_PACKET;
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end
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if (header_done) fwd_input <= 1;
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header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
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end
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end
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//
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// Forward this packet to XO only
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//
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FORWARD_XO: begin
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if (out_tvalid && out_tready) begin
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if (out_tlast) begin
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state <= WAIT_PACKET;
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end
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if (header_done) fwd_input <= 1;
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header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
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end
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end
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//
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// Forward this packet to the Radio Core only
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//
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FORWARD_RADIO_CORE: begin
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if (out_tvalid && out_tready) begin
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if (out_tlast) begin
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state <= WAIT_PACKET;
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end
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if (header_done) fwd_input <= 1;
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header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
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end
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end
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//
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// Drop this packet on the ground
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//
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DROP_PACKET: begin
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if (out_tvalid && out_tready) begin
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if (out_tlast) begin
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state <= WAIT_PACKET;
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end
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if (header_done) fwd_input <= 1;
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header_ram_addr <= out_tlast? 4'b0 : header_ram_addr + 1;
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end
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end
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endcase // case (state)
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end // else: !if(reset || clear)
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//
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// Classifier State machine.
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// Deep packet inspection during header ingress.
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//
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always @(posedge clk)
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if (reset || clear) begin
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is_eth_dst_addr <= 1'b0;
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is_eth_broadcast <= 1'b0;
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is_eth_type_ipv4 <= 1'b0;
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is_ipv4_dst_addr <= 1'b0;
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is_ipv4_proto_udp <= 1'b0;
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is_ipv4_proto_icmp <= 1'b0;
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is_udp_dst_ports <= 0;
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is_icmp_no_fwd <= 0;
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is_chdr <= 1'b0;
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// space_in_fifo <= 0;
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// is_there_fifo_space <= 1;
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// packet_length <= 0;
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end else if (in_tvalid && in_tready) begin // if (reset || clear)
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in_tdata_reg <= in_tdata;
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case (header_ram_addr)
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// Pipelined, so nothing to look at first cycle.
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// Reset all the flags here.
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0: begin
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is_eth_dst_addr <= 1'b0;
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is_eth_broadcast <= 1'b0;
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is_eth_type_ipv4 <= 1'b0;
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is_ipv4_dst_addr <= 1'b0;
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is_ipv4_proto_udp <= 1'b0;
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is_ipv4_proto_icmp <= 1'b0;
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is_udp_dst_ports <= 0;
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is_icmp_no_fwd <= 0;
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is_chdr <= 1'b0;
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end
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1: begin
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// Look at upper 16bits of MAC Dst Addr.
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if (in_tdata_reg[15:0] == 16'hFFFF)
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is_eth_broadcast <= 1'b1;
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if (in_tdata_reg[15:0] == my_mac[47:32])
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is_eth_dst_addr <= 1'b1;
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end
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2: begin
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// Look at lower 32bits of MAC Dst Addr.
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if (is_eth_broadcast && (in_tdata_reg[63:32] == 32'hFFFFFFFF))
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is_eth_broadcast <= 1'b1;
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else
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is_eth_broadcast <= 1'b0;
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if (is_eth_dst_addr && (in_tdata_reg[63:32] == my_mac[31:0]))
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is_eth_dst_addr <= 1'b1;
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else
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is_eth_dst_addr <= 1'b0;
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end // case: 2
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3: begin
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// Look at Ethertype
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if (in_tdata_reg[47:32] == 16'h0800)
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is_eth_type_ipv4 <= 1'b1;
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// Extract Packet Length
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// ADD THIS HERE.
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end
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4: begin
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// Look at protocol enapsulated by IPv4
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if ((in_tdata_reg[23:16] == 8'h11) && is_eth_type_ipv4)
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is_ipv4_proto_udp <= 1'b1;
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if ((in_tdata_reg[23:16] == 8'h01) && is_eth_type_ipv4)
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is_ipv4_proto_icmp <= 1'b1;
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end
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5: begin
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// Look at IP DST Address.
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if ((in_tdata_reg[31:0] == my_ip[31:0]) && is_eth_type_ipv4)
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is_ipv4_dst_addr <= 1'b1;
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end
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6: begin
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// Look at UDP dest port
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if ((in_tdata_reg[47:32] == my_port0[15:0]) && is_ipv4_proto_udp)
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is_udp_dst_ports[0] <= 1'b1;
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if ((in_tdata_reg[47:32] == my_port1[15:0]) && is_ipv4_proto_udp)
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is_udp_dst_ports[1] <= 1'b1;
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// Look at ICMP type and code
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if (in_tdata_reg[63:48] == {my_icmp_type, my_icmp_code} && is_ipv4_proto_icmp)
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is_icmp_no_fwd <= 1'b1;
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end
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7: begin
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// Look for a possible CHDR header string
|
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if (in_tdata_reg[63:32] != 32'h0)
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is_chdr <= 1'b1;
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end
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8: begin
|
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// Check VRT Stream ID
|
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// ADD THIS HERE.
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end
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endcase // case (header_ram_addr)
|
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end // if (in_tvalid && in_tready)
|
||||
|
||||
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||||
//
|
||||
// Output (Egress) Interface muxing
|
||||
//
|
||||
assign out_tready =
|
||||
(state == DROP_PACKET) ||
|
||||
((state == FORWARD_RADIO_CORE) && vita_pre_tready) ||
|
||||
((state == FORWARD_XO) && xo_pre_tready) ||
|
||||
((state == FORWARD_ZPU) && zpu_pre_tready) ||
|
||||
((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready && xo_pre_tready);
|
||||
|
||||
assign out_tvalid = ((state == FORWARD_RADIO_CORE) ||
|
||||
(state == FORWARD_XO) ||
|
||||
(state == FORWARD_ZPU) ||
|
||||
(state == FORWARD_ZPU_AND_XO) ||
|
||||
(state == DROP_PACKET)) && (!fwd_input || in_tvalid);
|
||||
|
||||
assign {out_tlast,out_tuser,out_tdata} = fwd_input ? {in_tlast,in_tuser,in_tdata} : header_ram[header_ram_addr];
|
||||
|
||||
assign in_tready = (state == WAIT_PACKET) ||
|
||||
(state == READ_HEADER) ||
|
||||
(state == DROP_PACKET) ||
|
||||
(out_tready && fwd_input);
|
||||
|
||||
|
||||
// Because we can forward to both the ZPU and XO FIFO's concurrently
|
||||
// we have to make sure both can accept data in the same cycle.
|
||||
// This makes it possible for either destination to block the other.
|
||||
assign xo_pre_tvalid = out_tvalid &&
|
||||
((state == FORWARD_XO) ||
|
||||
((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready));
|
||||
assign zpu_pre_tvalid = out_tvalid &&
|
||||
((state == FORWARD_ZPU) ||
|
||||
((state == FORWARD_ZPU_AND_XO) && xo_pre_tready));
|
||||
assign vita_pre_tvalid = out_tvalid && (state == FORWARD_RADIO_CORE);
|
||||
|
||||
assign {zpu_pre_tuser,zpu_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_ZPU)) ?
|
||||
{out_tuser,out_tdata} : 0;
|
||||
|
||||
assign {xo_pre_tuser,xo_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_XO)) ?
|
||||
{out_tuser,out_tdata} : 0;
|
||||
|
||||
assign {vita_pre_tuser,vita_pre_tdata} = (state == FORWARD_RADIO_CORE) ? {out_tuser,out_tdata} : 0;
|
||||
|
||||
assign zpu_pre_tlast = out_tlast && ((state == FORWARD_ZPU) || (state == FORWARD_ZPU_AND_XO));
|
||||
|
||||
assign xo_pre_tlast = out_tlast && ((state == FORWARD_XO) || (state == FORWARD_ZPU_AND_XO));
|
||||
|
||||
assign vita_pre_tlast = out_tlast && (state == FORWARD_RADIO_CORE);
|
||||
|
||||
//
|
||||
// Egress FIFO's (Large)
|
||||
//
|
||||
axi_fifo #(.WIDTH(69),.SIZE(10))
|
||||
axi_fifo_zpu (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.clear(clear),
|
||||
.i_tdata({zpu_pre_tlast,zpu_pre_tuser,zpu_pre_tdata}),
|
||||
.i_tvalid(zpu_pre_tvalid),
|
||||
.i_tready(zpu_pre_tready),
|
||||
.o_tdata({zpu_tlast,zpu_tuser,zpu_tdata}),
|
||||
.o_tvalid(zpu_tvalid),
|
||||
.o_tready(zpu_tready),
|
||||
.space(),
|
||||
.occupied()
|
||||
);
|
||||
|
||||
axi_fifo #(.WIDTH(69),.SIZE(10))
|
||||
axi_fifo_xo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.clear(clear),
|
||||
.i_tdata({xo_pre_tlast,xo_pre_tuser,xo_pre_tdata}),
|
||||
.i_tvalid(xo_pre_tvalid),
|
||||
.i_tready(xo_pre_tready),
|
||||
.o_tdata({xo_tlast,xo_tuser,xo_tdata}),
|
||||
.o_tvalid(xo_tvalid),
|
||||
.o_tready(xo_tready),
|
||||
.space(),
|
||||
.occupied()
|
||||
);
|
||||
|
||||
axi_fifo #(.WIDTH(69),.SIZE(10))
|
||||
axi_fifo_vita (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.clear(clear),
|
||||
.i_tdata({vita_pre_tlast,vita_pre_tuser,vita_pre_tdata}),
|
||||
.i_tvalid(vita_pre_tvalid),
|
||||
.i_tready(vita_pre_tready),
|
||||
.o_tdata({vita_tlast,vita_tuser,vita_tdata}),
|
||||
.o_tvalid(vita_tvalid),
|
||||
.o_tready(vita_tready),
|
||||
.space(),
|
||||
.occupied()
|
||||
);
|
||||
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
|
||||
wire vready, zready, oready;
|
||||
wire vvalid, zvalid, ovalid;
|
||||
|
||||
reg [2:0] ed_state;
|
||||
localparam ED_IDLE = 3'd0;
|
||||
localparam ED_IN_HDR = 3'd1;
|
||||
localparam ED_VITA = 3'd2;
|
||||
localparam ED_ZPU = 3'd3;
|
||||
localparam ED_OUT = 3'd4;
|
||||
localparam ED_DROP = 3'd5;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
// for now, send everything to zpu
|
||||
/*
|
||||
always @(posedge clk)
|
||||
if(reset | clear)
|
||||
ed_state <= ED_IDLE;
|
||||
else
|
||||
case(ed_state)
|
||||
ED_IDLE:
|
||||
if(vready & zready & oready & in_tvalid)
|
||||
;
|
||||
endcase // case (ed_state)
|
||||
*/
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
axi_packet_gate #(.WIDTH(64), .SIZE(10)) vita_gate
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.i_tdata(in_tdata), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(vready),
|
||||
.o_tdata(vita_tdata), .o_tlast(vita_tlast), .o_tvalid(vita_tvalid), .o_tready(vita_tready));
|
||||
|
||||
axi_packet_gate #(.WIDTH(68), .SIZE(10)) zpu_gate
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.i_tdata({in_tuser,in_tdata}), .i_tlast(in_tlast), .i_terror(in_tuser[3]), .i_tvalid(in_tvalid), .i_tready(in_tready),
|
||||
.o_tdata({zpu_tuser,zpu_tdata}), .o_tlast(zpu_tlast), .o_tvalid(zpu_tvalid), .o_tready(zpu_tready));
|
||||
|
||||
axi_packet_gate #(.WIDTH(68), .SIZE(10)) out_gate
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.i_tdata({in_tuser,in_tdata}), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(oready),
|
||||
.o_tdata({out_tuser,out_tdata}), .o_tlast(out_tlast), .o_tvalid(out_tvalid), .o_tready(out_tready));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
endmodule // eth_dispatch
|
||||
Reference in New Issue
Block a user