Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
@@ -0,0 +1,13 @@
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#
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# Copyright 2010-2013 Ettus Research LLC
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#
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##################################################
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# SERDES Sources
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##################################################
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GPIF2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/gpif2/, \
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gpif2_slave_fifo32.v \
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gpif2_to_fifo64.v \
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fifo64_to_gpif2.v \
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gpif2_error_checker.v \
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))
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@@ -0,0 +1,64 @@
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//
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// Copyright 2012-2013 Ettus Research LLC
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//
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module fifo64_to_gpif2
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#(
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parameter FIFO_SIZE = 9
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)
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(
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//input fifo interface
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input fifo_clk, input fifo_rst,
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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//output interface
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input gpif_clk, input gpif_rst,
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output [31:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready
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);
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wire [31:0] i32_tdata;
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wire i32_tlast;
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wire i32_tvalid, i32_tready;
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axi_fifo64_to_fifo32 fifo64_to_fifo32
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(
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.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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.i_tdata(i_tdata), .i_tuser(3'b0/*done care*/), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(i32_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(i32_tlast), .o_tvalid(i32_tvalid), .o_tready(i32_tready)
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);
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wire [31:0] gate_tdata;
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wire gate_tlast;
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wire gate_tvalid, gate_tready;
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axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
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(
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.reset(fifo_rst | gpif_rst),
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.i_aclk(fifo_clk), .i_tdata({i32_tlast, i32_tdata}), .i_tvalid(i32_tvalid), .i_tready(i32_tready),
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.o_aclk(gpif_clk), .o_tdata({gate_tlast, gate_tdata}), .o_tvalid(gate_tvalid), .o_tready(gate_tready)
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);
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wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
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axi_packet_gate #(.WIDTH(32), .SIZE(FIFO_SIZE)) buffer_whole_pkt
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(
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.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
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.i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
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.o_tdata(int0_tdata), .o_tlast(int0_tlast), .o_tvalid(int0_tvalid), .o_tready(int0_tready)
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);
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axi_fifo #(.WIDTH(33), .SIZE(0)) outgress_timing_fifo
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(
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.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
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.i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(),
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.o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready), .occupied()
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);
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endmodule //fifo_to_gpmc16
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@@ -0,0 +1,126 @@
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// Copyright 2013 Ettus Research LLC
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// inspect the input for invalid conditions
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// when bad - drain input, flag error, and insert error msg packet
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//
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// Packets alignment errors are searched for in two different ways:
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// 1) Blatently illegal values in what is assumed to be the PACKET_LENGTH field
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// in the CHDR header
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// (We could probably improve this by looking at other fields of the header that
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// have a limited range of values)
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// 2) Packet length indicating an EOF word that doesn't have TLAST set in the FIFO.
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// (Upstream can howvever legally insert TLAST in the FIFO for words that are not EOF)
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//
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// Packet allignment recovery strategy is to wait for TLAST asserted and then decode the
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// following data assuming it is the start of new CHDR headers.
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//
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//TODO - insert bad packet
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module gpif2_error_checker
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#(parameter SIZE = 9)
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(input clk, input reset, input clear,
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input [31:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
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output [31:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
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output bus_error, output [63:0] debug);
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wire [31:0] gate_tdata;
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wire gate_tlast, gate_terror;
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wire gate_tvalid, gate_tready;
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localparam STATE_HDR = 0;
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localparam STATE_FWD = 1;
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localparam STATE_EOF = 2;
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localparam STATE_WAIT = 3;
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reg [1:0] state;
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reg [15:0] lines32;
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reg [11:0] seq_id_ref;
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reg seq_id_bad;
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reg seq_id_wayoff;
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wire [15:0] hdr_bytes = i_tdata[15:0] + 3; //round up to multiple of 4
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wire [15:0] hdr_lines32 = {2'b0, hdr_bytes[15:2]}; //convert to lines32 count
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wire [11:0] seq_id_actual = i_tdata[27:16];
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wire obviously_bad_hdr = (hdr_lines32 == 16'h0) || (hdr_lines32 > (1 << SIZE));
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always @(posedge clk) begin
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if (reset | clear) begin
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state <= STATE_HDR;
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lines32 <= 16'b0;
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seq_id_ref <= 12'h0;
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seq_id_bad <= 0;
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seq_id_wayoff <= 0;
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end
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else case (state)
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STATE_HDR: begin //forward header and grab vita length
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if (i_tvalid && i_tready) begin
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if (obviously_bad_hdr) state <= STATE_WAIT;
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else if (hdr_lines32 == 16'h1) state <= STATE_HDR;
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else if (hdr_lines32 == 16'h2) state <= STATE_EOF;
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else state <= STATE_FWD;
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seq_id_bad <= (seq_id_actual != seq_id_ref);
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seq_id_wayoff <= (seq_id_actual != seq_id_ref) |
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(seq_id_actual != seq_id_ref+1) |
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(seq_id_actual != seq_id_ref+2) |
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(seq_id_actual != seq_id_ref+3);
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if (seq_id_actual != seq_id_ref)
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seq_id_ref <= seq_id_actual + 1;
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else
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seq_id_ref <= seq_id_ref + 1;
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end
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lines32 <= hdr_lines32;
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end
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STATE_FWD: begin //forward the rest of vita packet
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if (i_tvalid && i_tready) begin
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if (lines32 == 16'h3) state <= STATE_EOF;
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lines32 <= lines32 - 1'b1;
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end
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end
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STATE_EOF: begin //do last line of vita frame + eof
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if (i_tvalid && i_tready)
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if (gate_tlast) state <= STATE_HDR;
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else state <= STATE_WAIT; // Try somehow to get synchronized again.
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end
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STATE_WAIT: begin //drop until idle
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if (i_tvalid && i_tready && i_tlast) state <= STATE_HDR;
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end
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endcase //state
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end
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assign bus_error = (gate_terror && gate_tvalid && gate_tready) || ((state == STATE_HDR) && i_tvalid && i_tready && obviously_bad_hdr);
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assign gate_tlast = (state == STATE_HDR)? (hdr_lines32 == 16'h1) : (state == STATE_EOF);
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assign gate_tdata = i_tdata;
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assign gate_tvalid = i_tvalid && ((state == STATE_HDR)? !obviously_bad_hdr : (state != STATE_WAIT));
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assign i_tready = gate_tready;
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axi_packet_gate #(.WIDTH(32), .SIZE(SIZE)) gate_xfer
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(
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.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(gate_tdata), .i_tlast(gate_tlast), .i_terror(1'b0), .i_tvalid(gate_tvalid), .i_tready(gate_tready),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
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);
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assign debug = {13'b0,
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seq_id_wayoff, //[50] [114]
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gate_terror, // [49] [113]
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obviously_bad_hdr, // [48] [112]
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seq_id_bad, // [47] [111]
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seq_id_ref, // [46:35] [110:99]
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i_tlast, // [34] [98]
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i_tready, // [33] [97]
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i_tvalid, // [32] [96]
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i_tdata}; // [31:0] [95:64]
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endmodule // cvita_insert_tlast
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@@ -0,0 +1,375 @@
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//
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// Copyright 2011-2013 Ettus Research LLC
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//
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//////////////////////////////////////////////////////////////////////////////////
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//this is a FIFO master interface for the FX3 in "slave fifo" mode.
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module gpif2_slave_fifo32
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#(
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//sizes for fifo64 2 clock cascade fifos
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parameter DATA_RX_FIFO_SIZE = 12, //max vita pkt size
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parameter DATA_TX_FIFO_SIZE = 12, //max vita pkt size
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parameter CTRL_RX_FIFO_SIZE = 5, //small resp packets
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parameter CTRL_TX_FIFO_SIZE = 5, //small ctrl packets
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//address constants for the endpoints
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parameter ADDR_DATA_TX = 2'b00,
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parameter ADDR_DATA_RX = 2'b01,
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parameter ADDR_CTRL_TX = 2'b10,
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parameter ADDR_CTRL_RX = 2'b11,
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parameter END_WITH_COMMA = 0
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)
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(// GPIF signals
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input gpif_clk, input gpif_rst, input gpif_enb,
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inout [31:0] gpif_d,
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input [3:0] gpif_ctl,
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output reg sloe,
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output reg slrd,
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output reg slwr,
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output slcs,
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output reg pktend,
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output reg [1:0] fifoadr,
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// FIFO interfaces
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input fifo_clk, input fifo_rst,
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output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready,
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input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready,
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output [63:0] ctrl_tdata, output ctrl_tlast, output ctrl_tvalid, input ctrl_tready,
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input [63:0] resp_tdata, input resp_tlast, input resp_tvalid, output resp_tready,
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output [31:0] debug
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);
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reg fifo_nearly_full;
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wire ctrl_tx_fifo_nearly_full, data_tx_fifo_nearly_full;
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wire ctrl_tx_fifo_has_space, data_tx_fifo_has_space;
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wire [159:0] debug_tx_data, debug_tx_ctrl;
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assign slcs = 1'b0;
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//DMA FIFO ready and watermark flags
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reg EP_READY, EP_READY1, EP_WMARK, EP_WMARK1;
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always @(posedge gpif_clk) EP_READY <= gpif_ctl[0];
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always @(posedge gpif_clk) EP_WMARK <= gpif_ctl[1];
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always @(posedge gpif_clk) EP_READY1 <= EP_READY;
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always @(posedge gpif_clk) EP_WMARK1 <= EP_WMARK;
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// GPIF output data lines, tristate
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reg [31:0] gpif_data_in, gpif_data_out;
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always @(posedge gpif_clk) gpif_data_in <= gpif_d;
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assign gpif_d = sloe ? gpif_data_out[31:0] : 32'bz;
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// ////////////////////////////////////////////////////////////////////
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// GPIF bus master state machine
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wire wr_fifo_xfer, wr_fifo_eof;
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wire [31:0] wr_fifo_data;
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reg read_ready_go, write_ready_go;
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reg wr_one, rd_one;
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reg [3:0] state; //state machine current state
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localparam STATE_IDLE = 0;
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localparam STATE_THINK = 1;
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localparam STATE_READ = 2;
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localparam STATE_WRITE = 3;
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localparam STATE_WAIT = 4;
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reg [2:0] idle_cycles;
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reg [1:0] last_addr, next_addr;
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wire local_fifo_ready;
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reg slrd1, slrd2, slrd3;
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always @(posedge gpif_clk)
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if (gpif_rst) begin
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slrd1 <= 1;
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slrd2 <= 1;
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slrd3 <= 1;
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end else begin
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slrd1 <= slrd;
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slrd2 <= slrd1;
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slrd3 <= slrd2;
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end
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wire RD_VALID = ~slrd3;
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wire RD_LAST = slrd2;
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wire WR_VALID = (EP_WMARK1 || !wr_one);
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// //////////////////////////////////////////////////////////////
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// FX2 slave FIFO bus master state machine
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//
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always @(posedge gpif_clk)
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if(gpif_rst) begin
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state <= STATE_IDLE;
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sloe <= 0;
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slrd <= 1;
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slwr <= 1;
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pktend <= 1;
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gpif_data_out <= 32'b0;
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idle_cycles <= 0;
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fifoadr <= 0;
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wr_one <= 1'b0;
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rd_one <= 1'b0;
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last_addr <= 2'b0;
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end
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else if (gpif_enb) begin
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case (state)
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//
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// Increment fifoadr to point at next thread, set all strobes to idle,
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//
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STATE_IDLE: begin
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sloe <= 0;
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slrd <= 1;
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slwr <= 1;
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pktend <= 1;
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gpif_data_out <= 32'b0;
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fifoadr <= next_addr;
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state <= STATE_WAIT;
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idle_cycles <= 0;
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end
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//
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// now wait here for 8 clock cycles before transitioning to STATE_THINK.
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// We stay in this state if no local FIFO's can proceed at this point.
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//
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STATE_WAIT: begin
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if (local_fifo_ready) begin
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idle_cycles <= idle_cycles + 1'b1;
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if (idle_cycles == 3'b111) state <= STATE_THINK;
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end
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else begin
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idle_cycles <= 3'b0;
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fifoadr <= fifoadr + 2'b1;
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end
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end
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//
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// If there is a read to start, assert SLRD and SLOE and transition to STATE_READ.
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// If there is a write to perform, set flags that says there is the possibility to do at least
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// one write (wr_one) and transition to STATE_WRITE
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//
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STATE_THINK: begin
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if (EP_READY1 && read_ready_go) begin
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state <= STATE_READ;
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slrd <= 0;
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rd_one <= 0;
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end
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else if (EP_READY1 && write_ready_go) begin
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state <= STATE_WRITE;
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sloe <= 1;
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wr_one <= 1'b0;
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end
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else begin
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state <= STATE_IDLE;
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end
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idle_cycles <= 0;
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last_addr <= fifoadr;
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end
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// If flag rd_one is set (armed 5 cycles after slrd goes initialy assrted) and RD_VALID has gone deasserted
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// (meaning that the watermark deasserted 5 clock cycles ago) transition to STATE_IDLE.
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// If watermark deasserted 2 cycles ago de-assert slrd ...read data is still traveling in the pipeline.
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// Whilst RD_VALID stays asserted keep the rd_one flag armed.
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STATE_READ: begin
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if (rd_one && ~RD_VALID) state <= STATE_IDLE;
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if (~EP_WMARK1 | fifo_nearly_full) slrd <= 1;
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if (RD_VALID) rd_one <= 1'b1;
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end
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// If local FIFO goes empty or tlast is set then transition to STATE_IDLE
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// Push local FIFO data out onto GPIF data bus.
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// if local FIFO has valid data then assert slwr
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// if local FIFO assertes tlast then assert pktend
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// If WR_VALID asserted (because wr_one already asserted in the first cycle in this state)
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// now clear wr_one (watermark will keep WR_VALID asserted from now on if this is a burst).
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//
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STATE_WRITE: begin
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if (~wr_fifo_xfer || wr_fifo_eof) state <= STATE_IDLE;
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gpif_data_out <= wr_fifo_data;
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slwr <= ~wr_fifo_xfer;
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pktend <= ~wr_fifo_eof;
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if (WR_VALID) wr_one <= 1'b1;
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end
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default: state <= STATE_IDLE;
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endcase
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end
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// ///////////////////////////////////////////////////////////////////
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// fifo signal assignments and enables
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//output from fifos - ready to xfer
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wire data_tx_tready, ctrl_tx_tready;
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wire ctrl_rx_tvalid, data_rx_tvalid;
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//Priority encoding for the the next address to service:
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//The next address to service is based on the readiness
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//of the internal fifos and last serviced fairness metric.
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always @(posedge gpif_clk) next_addr <=
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((ctrl_rx_tvalid && last_addr != ADDR_CTRL_RX)? ADDR_CTRL_RX :
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((ctrl_tx_fifo_has_space && last_addr != ADDR_CTRL_TX)? ADDR_CTRL_TX :
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((data_rx_tvalid && last_addr != ADDR_DATA_RX)? ADDR_DATA_RX :
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((data_tx_fifo_has_space && last_addr != ADDR_DATA_TX)? ADDR_DATA_TX :
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(fifoadr + 2'b1)
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))));
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|
||||
//Help the FPGA search to only look for addrs that the FPGA is ready for
|
||||
assign local_fifo_ready =
|
||||
(ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
|
||||
(ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
|
||||
(data_rx_tvalid && (fifoadr == ADDR_DATA_RX)) ||
|
||||
(data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
|
||||
|
||||
always @(posedge gpif_clk) fifo_nearly_full <=
|
||||
(ctrl_tx_fifo_nearly_full && (fifoadr == ADDR_CTRL_TX)) ||
|
||||
(data_tx_fifo_nearly_full && (fifoadr == ADDR_DATA_TX));
|
||||
|
||||
always @(posedge gpif_clk) read_ready_go <=
|
||||
(ctrl_tx_fifo_has_space && (fifoadr == ADDR_CTRL_TX)) ||
|
||||
(data_tx_fifo_has_space && (fifoadr == ADDR_DATA_TX));
|
||||
|
||||
always @(posedge gpif_clk) write_ready_go <=
|
||||
(ctrl_rx_tvalid && (fifoadr == ADDR_CTRL_RX)) ||
|
||||
(data_rx_tvalid && (fifoadr == ADDR_DATA_RX));
|
||||
|
||||
//fifo xfer enable
|
||||
wire data_rx_tready = (state == STATE_WRITE) && (fifoadr == ADDR_DATA_RX) && WR_VALID;
|
||||
wire ctrl_rx_tready = (state == STATE_WRITE) && (fifoadr == ADDR_CTRL_RX) && WR_VALID;
|
||||
wire data_tx_tvalid = (state == STATE_READ) && (fifoadr == ADDR_DATA_TX) && RD_VALID;
|
||||
wire ctrl_tx_tvalid = (state == STATE_READ) && (fifoadr == ADDR_CTRL_TX) && RD_VALID;
|
||||
|
||||
//outputs from rx fifo paths
|
||||
wire ctrl_rx_tlast, data_rx_tlast;
|
||||
wire [31:0] ctrl_rx_tdata, data_rx_tdata;
|
||||
|
||||
//mux rx outputs for gpif state machine
|
||||
assign wr_fifo_xfer = (fifoadr == ADDR_CTRL_RX)? (ctrl_rx_tvalid && ctrl_rx_tready) : (data_rx_tvalid && data_rx_tready);
|
||||
assign wr_fifo_eof = wr_fifo_xfer && ((fifoadr == ADDR_CTRL_RX)? ctrl_rx_tlast : data_rx_tlast);
|
||||
assign wr_fifo_data = (fifoadr == ADDR_CTRL_RX)? ctrl_rx_tdata : data_rx_tdata;
|
||||
|
||||
wire ctrl_bus_error, tx_bus_error;
|
||||
|
||||
// ////////////////////////////////////////////////////////////////////
|
||||
// TX Data Path
|
||||
|
||||
gpif2_to_fifo64 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE)) gpif2_to_fifo64_tx(
|
||||
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
|
||||
.i_tdata(gpif_data_in), .i_tlast(RD_LAST), .i_tvalid(data_tx_tvalid), .i_tready(data_tx_tready),
|
||||
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
|
||||
.fifo_nearly_full(data_tx_fifo_nearly_full), .fifo_has_space(data_tx_fifo_has_space),
|
||||
.o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready),
|
||||
.bus_error(tx_bus_error), .debug(debug_tx_data)
|
||||
);
|
||||
|
||||
// ////////////////////////////////////////////
|
||||
// RX Data Path
|
||||
|
||||
fifo64_to_gpif2 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo64_to_gpif2_rx(
|
||||
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
|
||||
.i_tdata(rx_tdata), .i_tlast(rx_tlast), .i_tvalid(rx_tvalid), .i_tready(rx_tready),
|
||||
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
|
||||
.o_tdata(data_rx_tdata), .o_tlast(data_rx_tlast), .o_tvalid(data_rx_tvalid), .o_tready(data_rx_tready)
|
||||
);
|
||||
|
||||
// ////////////////////////////////////////////////////////////////////
|
||||
// CTRL path
|
||||
|
||||
gpif2_to_fifo64 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE)) gpif2_to_fifo64_ctrl(
|
||||
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
|
||||
.i_tdata(gpif_data_in), .i_tlast(RD_LAST), .i_tvalid(ctrl_tx_tvalid), .i_tready(ctrl_tx_tready),
|
||||
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
|
||||
.fifo_nearly_full(ctrl_tx_fifo_nearly_full), .fifo_has_space(ctrl_tx_fifo_has_space),
|
||||
.o_tdata(ctrl_tdata), .o_tlast(ctrl_tlast), .o_tvalid(ctrl_tvalid), .o_tready(ctrl_tready),
|
||||
.bus_error(ctrl_bus_error), .debug(debug_tx_ctrl)
|
||||
);
|
||||
|
||||
// ////////////////////////////////////////////////////////////////////
|
||||
// RESP path
|
||||
|
||||
fifo64_to_gpif2 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo64_to_gpif2_resp(
|
||||
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
|
||||
.i_tdata(resp_tdata), .i_tlast(resp_tlast), .i_tvalid(resp_tvalid), .i_tready(resp_tready),
|
||||
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
|
||||
.o_tdata(ctrl_rx_tdata), .o_tlast(ctrl_rx_tlast), .o_tvalid(ctrl_rx_tvalid), .o_tready(ctrl_rx_tready)
|
||||
);
|
||||
|
||||
// ////////////////////////////////////////////
|
||||
// DEBUG
|
||||
|
||||
wire [31:0] debug0 = {
|
||||
sloe, slrd, slwr, pktend, fifoadr, EP_READY, EP_WMARK, //8
|
||||
state, //4
|
||||
data_tx_tvalid, data_tx_tready, data_rx_tvalid, data_rx_tready, //4
|
||||
gpif_d[15:0] //16
|
||||
};
|
||||
|
||||
reg [31:0] debug_reg0;
|
||||
reg [31:0] debug_reg1;
|
||||
reg [31:0] debug_reg2;
|
||||
always @(posedge gpif_clk) debug_reg0 <= debug0;
|
||||
always @(posedge gpif_clk) debug_reg1 <= debug_reg0;
|
||||
always @(posedge gpif_clk) debug_reg2 <= debug_reg1;
|
||||
assign debug = debug_reg2;
|
||||
|
||||
wire [37:0] debug_resp = {
|
||||
resp_tlast, // 37
|
||||
resp_tready, // 36
|
||||
resp_tvalid, // 35
|
||||
ctrl_rx_tlast, // 34
|
||||
ctrl_rx_tready, // 33
|
||||
ctrl_rx_tvalid, // 32
|
||||
ctrl_rx_tdata // 31:0
|
||||
};
|
||||
|
||||
|
||||
reg [255:0] debug1,debug2;
|
||||
|
||||
always @(posedge gpif_clk) debug1 <= {debug_resp,debug_tx_ctrl,debug0};
|
||||
always @(posedge gpif_clk) debug2 <= debug1;
|
||||
|
||||
|
||||
|
||||
wire [35:0] CONTROL0,CONTROL1;
|
||||
/*
|
||||
chipscope_ila_32 chipscope_ila_32(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(gpif_clk), // IN
|
||||
.TRIG0(debug2) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
chipscope_ila_128 chipscope_ila_128(
|
||||
.CONTROL(CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK(fifo_clk), // IN
|
||||
.TRIG0({debug4,debug6}) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
|
||||
chipscope_ila_256 chipscope_ila_256(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(gpif_clk), // IN
|
||||
.TRIG0(debug2) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
chipscope_ila_32 chipscope_ila_32_2(
|
||||
.CONTROL(CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK(gpif_clk), // IN
|
||||
.TRIG0(32'd0) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
chipscope_icon chipscope_icon(
|
||||
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
*/
|
||||
endmodule // gpif2_slave_fifo32
|
||||
@@ -0,0 +1,118 @@
|
||||
//
|
||||
// Copyright 2012-2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
|
||||
module gpif2_to_fifo64
|
||||
#(
|
||||
parameter FIFO_SIZE = 9
|
||||
)
|
||||
(
|
||||
//input interface
|
||||
input gpif_clk, input gpif_rst,
|
||||
input [31:0] i_tdata,
|
||||
input i_tlast,
|
||||
input i_tvalid,
|
||||
output i_tready,
|
||||
output fifo_has_space,
|
||||
output fifo_nearly_full,
|
||||
|
||||
//output fifo interface
|
||||
input fifo_clk, input fifo_rst,
|
||||
output [63:0] o_tdata,
|
||||
output o_tlast,
|
||||
output o_tvalid,
|
||||
input o_tready,
|
||||
|
||||
output bus_error,
|
||||
output [159:0] debug
|
||||
);
|
||||
|
||||
wire [31:0] int_tdata;
|
||||
wire int_tlast;
|
||||
wire int_tvalid, int_tready;
|
||||
|
||||
wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
|
||||
|
||||
//this fifo provides a space signal so we know a burst is possible
|
||||
localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8;
|
||||
wire [15:0] space;
|
||||
|
||||
|
||||
assign fifo_has_space = space >= (1 << BURST_SIZE);
|
||||
assign fifo_nearly_full = (space < 6); // 5 spaces left.
|
||||
|
||||
axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo
|
||||
(
|
||||
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
|
||||
.i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(),
|
||||
.o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied()
|
||||
);
|
||||
axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff
|
||||
(
|
||||
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
|
||||
.i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space),
|
||||
.o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied()
|
||||
);
|
||||
|
||||
reg input_write_error;
|
||||
|
||||
always @(posedge gpif_clk) input_write_error <= i_tvalid & ~i_tready;
|
||||
|
||||
|
||||
wire [31:0] chk_tdata;
|
||||
wire chk_tlast;
|
||||
wire chk_tvalid, chk_tready;
|
||||
|
||||
axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
|
||||
(
|
||||
.reset(fifo_rst | gpif_rst),
|
||||
.i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
|
||||
.o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready)
|
||||
);
|
||||
|
||||
wire [31:0] o32_tdata;
|
||||
wire o32_tlast;
|
||||
wire o32_tvalid, o32_tready;
|
||||
|
||||
//reframes a tlast from the vita header - and drops bad packets
|
||||
//*
|
||||
gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker
|
||||
(
|
||||
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
|
||||
.i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready),
|
||||
.o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready),
|
||||
.bus_error(bus_error), .debug(debug[63:0])
|
||||
);
|
||||
//*/
|
||||
//assign o32_tdata = chk_tdata;
|
||||
//assign o32_tlast = chk_tlast;
|
||||
//assign o32_tvalid = chk_tvalid;
|
||||
//assign chk_tready = o32_tready;
|
||||
|
||||
axi_fifo32_to_fifo64 fifo32_to_fifo64
|
||||
(
|
||||
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
|
||||
.i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready),
|
||||
.o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
|
||||
);
|
||||
|
||||
assign debug[159:64] = {
|
||||
fifo_nearly_full, // 146
|
||||
space[9:0], // 145:136
|
||||
input_write_error, // 135
|
||||
int_tlast, // 134
|
||||
int_tready, // 133
|
||||
int_tvalid, // 132
|
||||
i_tlast, // 131
|
||||
i_tready, // 130
|
||||
fifo_has_space, // 129
|
||||
i_tvalid, // 128
|
||||
int_tdata[31:0], // 127:96
|
||||
i_tdata[31:0] // 95:64
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule //fifo_to_gpif2
|
||||
Reference in New Issue
Block a user