Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
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//
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// Copyright 2011-2013 Ettus Research LLC
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//
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//! The USRP digital up-conversion chain
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module duc_chain
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#(
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parameter BASE = 0,
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parameter DSPNO = 0,
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parameter WIDTH = 24
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)
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(input clk, input rst, input clr,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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// To TX frontend
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output [WIDTH-1:0] tx_fe_i,
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output [WIDTH-1:0] tx_fe_q,
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// From TX control
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input [31:0] sample,
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input run,
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output strobe,
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output [31:0] debug
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);
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wire [17:0] scale_factor;
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wire [31:0] phase_inc;
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reg [31:0] phase;
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wire [7:0] interp_rate;
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wire [3:0] tx_femux_a, tx_femux_b;
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wire enable_hb1, enable_hb2;
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wire rate_change;
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setting_reg #(.my_addr(BASE+0)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_inc),.changed());
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setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(scale_factor),.changed());
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setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));
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// Strobes are all now delayed by 1 cycle for timing reasons
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wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
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reg strobe_cic = 1;
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reg strobe_hb1 = 1;
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reg strobe_hb2 = 1;
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assign strobe = strobe_hb1;
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cic_strober #(.WIDTH(8))
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cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
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.strobe_fast(1),.strobe_slow(strobe_cic_pre) );
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cic_strober #(.WIDTH(2))
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hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2 : 1),
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.strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
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cic_strober #(.WIDTH(2))
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hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2 : 1),
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.strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
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always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
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always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
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always @(posedge clk) strobe_cic <= strobe_cic_pre;
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// NCO
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always @(posedge clk)
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if(rst)
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phase <= 0;
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else if(~run)
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phase <= 0;
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else
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phase <= phase + phase_inc;
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wire signed [17:0] da, db;
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wire signed [35:0] prod_i, prod_q;
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assign tx_fe_i = prod_i[33:34-WIDTH];
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assign tx_fe_q = prod_q[33:34-WIDTH];
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wire [17:0] i_interp, q_interp;
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wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
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wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
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// Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
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// but the default case inside hb_interp handles this
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hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[31:16], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
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hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({sample[15:0], 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
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small_hb_int #(.WIDTH(18)) small_hb_interp_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
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.output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
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small_hb_int #(.WIDTH(18)) small_hb_interp_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
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.output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
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cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
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cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
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.strobe_in(strobe_cic),.strobe_out(1),
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.signal_in(hb2_i),.signal_out(i_interp));
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cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
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cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
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.strobe_in(strobe_cic),.strobe_out(1),
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.signal_in(hb2_q),.signal_out(q_interp));
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localparam cwidth = WIDTH; // was 18
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localparam zwidth = 24; // was 16
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wire [cwidth-1:0] da_c, db_c;
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cordic_z24 #(.bitwidth(cwidth))
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cordic(.clock(clk), .reset(rst), .enable(run),
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.xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
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.zi(phase[31:32-zwidth]),
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.xo(da_c),.yo(db_c),.zo() );
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MULT18X18S MULT18X18S_inst
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(.P(prod_i), // 36-bit multiplier output
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.A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
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.B(scale_factor), // 18-bit multiplier input
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.C(clk), // Clock input
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.CE(1), // Clock enable input
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.R(rst) // Synchronous reset input
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);
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MULT18X18S MULT18X18S_inst_2
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(.P(prod_q), // 36-bit multiplier output
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.A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
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.B(scale_factor), // 18-bit multiplier input
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.C(clk), // Clock input
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.CE(1), // Clock enable input
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.R(rst) // Synchronous reset input
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);
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assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
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endmodule // duc_chain
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