Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
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//
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// Copyright 2012 Ettus Research LLC
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//
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`define LOG2(N) (\
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N < 2 ? 0 : \
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N < 4 ? 1 : \
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N < 8 ? 2 : \
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N < 16 ? 3 : \
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N < 32 ? 4 : \
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N < 64 ? 5 : \
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N < 128 ? 6 : \
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N < 256 ? 7 : \
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N < 512 ? 8 : \
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N < 1024 ? 9 : \
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10)
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module axi_crossbar
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#(
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parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
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parameter DST_WIDTH = 16, // Width of DST field we are routing on.
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parameter NUM_INPUTS = 2, // number of input AXI4-STREAM buses
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parameter NUM_OUTPUTS = 2 // number of output AXI4-STREAM buses
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)
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(
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input clk,
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input reset,
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input clear,
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input [7:0] local_addr,
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// Inputs
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input [(FIFO_WIDTH*NUM_INPUTS)-1:0] i_tdata,
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input [NUM_INPUTS-1:0] i_tvalid,
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input [NUM_INPUTS-1:0] i_tlast,
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output [NUM_INPUTS-1:0] i_tready,
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input [NUM_INPUTS-1:0] pkt_present,
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// Setting Bus
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input set_stb,
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input [15:0] set_addr,
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input [31:0] set_data,
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// Output
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output [(FIFO_WIDTH*NUM_OUTPUTS)-1:0] o_tdata,
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output [NUM_OUTPUTS-1:0] o_tvalid,
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output [NUM_OUTPUTS-1:0] o_tlast,
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input [NUM_OUTPUTS-1:0] o_tready,
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// readback bus
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input rb_rd_stb,
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input [`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:0] rb_addr,
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output [31:0] rb_data
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);
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genvar m,n;
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wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_in;
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wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_in;
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wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_valid_out;
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wire [(NUM_INPUTS*NUM_OUTPUTS)-1:0] forward_ack_out;
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wire [NUM_INPUTS-1:0] i_tready_slave [0:NUM_OUTPUTS-1];
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//
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// Instantiate an axi_slave_mux for every slave/output of the Crossbar switch.
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// Each axi_slave_mux contains logic to maux and resolve arbitration
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// for this particular slave/output.
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//
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generate
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for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: instantiate_slave_mux
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wire [NUM_INPUTS-1:0] i_tready_tmp;
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axi_slave_mux
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#(
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.FIFO_WIDTH(FIFO_WIDTH), // AXI4-STREAM data bus width
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.DST_WIDTH(DST_WIDTH), // Width of DST field we are routing on.
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.NUM_INPUTS(NUM_INPUTS) // number of input AXI buses
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) axi_slave_mux_i
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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// Inputs
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.i_tdata(i_tdata),
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.i_tvalid(i_tvalid),
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.i_tlast(i_tlast),
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.i_tready(i_tready_tmp),
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// Forwarding flags (One from each Input/Master)
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.forward_valid(forward_valid_in[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
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.forward_ack(forward_ack_out[(m+1)*NUM_INPUTS-1:m*NUM_INPUTS]),
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// Output
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.o_tdata(o_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
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.o_tvalid(o_tvalid[m]),
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.o_tlast(o_tlast[m]),
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.o_tready(o_tready[m])
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);
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if (m==0)
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assign i_tready_slave[0] = i_tready_tmp;
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else
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assign i_tready_slave[m] = i_tready_tmp | i_tready_slave[m-1] ;
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end // block: instantiate_slave_mux
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endgenerate
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assign i_tready = i_tready_slave[NUM_OUTPUTS-1];
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//
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// Permute the forwarding flag buses
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//
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generate
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for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: permute_outer
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for (n = 0; n < NUM_INPUTS; n = n + 1) begin: permute_inner
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assign forward_valid_in[n*NUM_OUTPUTS+m] = forward_valid_out[n+m*NUM_INPUTS];
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assign forward_ack_in[n+m*NUM_INPUTS] = forward_ack_out[n*NUM_OUTPUTS+m];
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end
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end
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endgenerate
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//
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// Instantiate an axi_forwarding_cam for every Input/Master of the Crossbar switch.
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// Each contains a TCAM like lookup that allocates an egress port.
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//
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wire [31:0] rb_data_mux[0:NUM_INPUTS-1];
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generate
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for (m = 0; m < NUM_INPUTS; m = m + 1) begin: instantiate_cam
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axi_forwarding_cam
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#(
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.BASE(0),
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.WIDTH(FIFO_WIDTH), // Bit width of FIFO word.
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.NUM_OUTPUTS(NUM_OUTPUTS)
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) axi_forwarding_cam_i
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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// Monitored FIFO signals
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.o_tdata(i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH]),
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.o_tvalid(i_tvalid[m]),
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.o_tready(i_tready[m]),
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.o_tlast(i_tlast[m]),
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.pkt_present(pkt_present[m]),
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// Configuration
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.local_addr(local_addr),
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// Setting Bus
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.set_stb(set_stb),
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.set_addr(set_addr),
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.set_data(set_data),
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// Header signals
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.forward_valid(forward_valid_out[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]),
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.forward_ack(forward_ack_in[(m+1)*NUM_OUTPUTS-1:m*NUM_OUTPUTS]),
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// Readback bus
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.rb_rd_stb(rb_rd_strobe && (rb_addr[`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:`LOG2(NUM_OUTPUTS)] == m)),
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.rb_addr(rb_addr[`LOG2(NUM_OUTPUTS)-1:0]),
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.rb_data(rb_data_mux[m])
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);
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end // block: instantiate_fifo_header
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endgenerate
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assign rb_data = rb_data_mux[rb_addr[`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)-1:`LOG2(NUM_OUTPUTS)]];
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endmodule // axi_crossbar
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