fpga: Change default MTU to 10

Original-commit: 7b7fa68880ca423ea3a47fc3dc97ba533921c9a5
2020-05-11 09:06:03 -05:00
parent 1de388c61b
commit c33b3779f9
5 changed files with 5 additions and 5 deletions
@@ -44,7 +44,7 @@ module axis_pyld_ctxt_to_chdr #(
  parameter SYNC_CLKS           = 0,
  parameter CONTEXT_FIFO_SIZE   = 1,
  parameter PAYLOAD_FIFO_SIZE   = 1,
-  parameter MTU                 = 9,
+  parameter MTU                 = 10,
  parameter CONTEXT_PREFETCH_EN = 1
 )(
  // Clock, reset and settings