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fpga: lib: Add AXI-Stream load split and merge modules

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Original-commit: 32fb626ef1b1d3078fd331143b03cd38d1e155f0
This commit is contained in:
Wade Fife
2025-02-14 15:59:19 -06:00
parent 72432c9278
commit bb2bfbfe95
6 changed files with 1058 additions and 0 deletions
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lib/sim/axi/axis_load_split_merge/Makefile
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#
# Copyright 2024 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one top-level module
SIM_TOP = axis_load_split_merge_all_tb
# Add test bench, user design under test, and
# additional user created files
SIM_SRCS = $(abspath \
axis_load_split_merge_tb.sv \
axis_load_split_merge_all_tb.sv \
)
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak