fpga: lib: Add AXI-Stream load split and merge modules
Original-commit: 32fb626ef1b1d3078fd331143b03cd38d1e155f0
This commit is contained in:
Wade Fife
@@ -0,0 +1,34 @@
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#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one top-level module
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SIM_TOP = axis_load_split_merge_all_tb
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# Add test bench, user design under test, and
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# additional user created files
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SIM_SRCS = $(abspath \
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axis_load_split_merge_tb.sv \
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axis_load_split_merge_all_tb.sv \
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)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,88 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_load_split_merge_all_tb
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//
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// Description:
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//
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// Top-level testbench for axis_load_split and axis_load_merge modules. This
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// instantiates multiple instances of axis_load_split_merge_tb to test
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// different configurations.
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//
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module axis_load_split_merge_all_tb;
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localparam int MAX_PKT_LEN = 16;
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localparam int INT_FIFO_SIZE = $clog2(MAX_PKT_LEN);
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localparam int DATA_W = 8;
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localparam int USER_W = 4;
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (4*DATA_W),
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.USER_W (USER_W),
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.USER_SEL (3),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (4),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(1)
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) tb_32b_to_4x8b();
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (2*DATA_W),
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.USER_W (USER_W),
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.USER_SEL (0),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (2),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(1)
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) tb_16b_to_2x8b();
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (4*DATA_W),
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.USER_W (USER_W),
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.USER_SEL (1),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (3),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(1)
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) tb_32b_to_3x8b();
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (4*DATA_W),
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.USER_W (USER_W),
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.USER_SEL (2),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (2),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(1)
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) tb_32b_to_2x8b();
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (DATA_W),
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.USER_W (USER_W),
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.USER_SEL (0),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (4),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(4)
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) tb_8b_to_4x8b();
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axis_load_split_merge_tb #(
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.MAX_PKT_LEN (MAX_PKT_LEN),
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.DATA_W (2*DATA_W),
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.USER_W (USER_W),
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.USER_SEL (0),
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.INT_DATA_W (DATA_W),
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.NUM_PORTS (4),
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.INT_FIFO_SIZE(INT_FIFO_SIZE),
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.EXT_FIFO_SIZE(4)
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) tb_16b_to_4x8b();
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endmodule
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@@ -0,0 +1,352 @@
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_load_split_merge_tb
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//
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// Description:
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//
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// Testbench for axis_load_split and axis_load_merge modules. It tests both
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// modules together but taking an input data stream and splitting it into
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// multiple streams, then combining them back together to recover the
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// original data stream.
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//
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// Parameters:
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//
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// MAX_PKT_LEN : Maximum packet length to test, in number of DATA_W words.
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// DATA_W : Width of the input data port to axis_load_split and the
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// output data port of axis_load_merge.
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// USER_W : Width of TUSER to test.
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// USER_SEL : USER_SEL value to test.
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// INT_DATA_W : Internal data width, at the output of axis_load_split and
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// the input to axis_load_merge.
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// NUM_PORTS : The number of ports to split into and merge.
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// INT_FIFO_SIZE : Log base 2 of the FIFO size (in units of DATA_W sized
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// words) to configure for the output FIFOs in
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// axis_load_split and the input FIFOs in axis_load_merge.
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// EXT_FIFO_SIZE : Log base 2 of the FIFO size (in units of DATA_W sized
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// words) to configure for the input FIFO in axis_load_split
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// and the output FIFO in axis_load_merge.
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//
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module axis_load_split_merge_tb #(
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int MAX_PKT_LEN = 16,
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int DATA_W = 32,
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int USER_W = 4,
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int USER_SEL = 0,
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int INT_DATA_W = 8,
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int NUM_PORTS = DATA_W/INT_DATA_W,
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int INT_FIFO_SIZE = $clog2(MAX_PKT_LEN),
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int EXT_FIFO_SIZE = 1
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);
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`include "test_exec.svh"
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`include "usrp_utils.svh"
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import PkgTestExec::*;
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import PkgAxiStreamBfm::*;
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import PkgRandom::*;
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// Use random or sequential data (easier for debug)
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localparam bit USE_RANDOM = 1;
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localparam real CLK_PER = 5;
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// Number of packets to test
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localparam NUM_PKTS = NUM_PORTS*100;
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// Width of packet count that's put in each packet
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localparam int PKT_COUNT_W = 8;
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if (INT_DATA_W < PKT_COUNT_W) begin : check_data_width
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$error("INT_DATA_W must be at least PKT_COUNT_W");
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end
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit clk;
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bit rst;
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sim_clock_gen #(.PERIOD(CLK_PER), .AUTOSTART(0))
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clk_gen (.clk(clk), .rst(rst));
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//---------------------------------------------------------------------------
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// Bus Functional Models
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//---------------------------------------------------------------------------
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// AXI-Stream Interfaces
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AxiStreamIf #(DATA_W, USER_W) i_axis (clk, rst);
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AxiStreamIf #(DATA_W, USER_W) o_axis (clk, rst);
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// AXI-Stream BFMs
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typedef AxiStreamBfm #(DATA_W, USER_W) bfm_t;
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typedef bfm_t::AxisPacket_t pkt_t;
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bfm_t bfm = new(i_axis, o_axis);
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//---------------------------------------------------------------------------
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// Device Under Test (DUT)
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//---------------------------------------------------------------------------
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logic [INT_DATA_W-1:0] split_tdata [NUM_PORTS];
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logic [ USER_W-1:0] split_tuser [NUM_PORTS];
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logic split_tlast [NUM_PORTS];
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logic split_tvalid [NUM_PORTS];
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logic split_tready [NUM_PORTS];
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// Convert the internal FIFO size from the external word size (DATA_W) to the
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// internal word size (INT_DATA_W).
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localparam int INT_WORD_FIFO_SIZE = INT_FIFO_SIZE + $clog2(DATA_W/INT_DATA_W);
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logic [USER_W-1:0] masked_tuser [NUM_PORTS];
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axis_load_split #(
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.IN_DATA_W (DATA_W ),
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.IN_FIFO_SIZE (EXT_FIFO_SIZE ),
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.OUT_DATA_W (INT_DATA_W ),
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.OUT_FIFO_SIZE(INT_WORD_FIFO_SIZE),
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.OUT_NUM_PORTS(NUM_PORTS ),
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.USER_W (USER_W )
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) axis_load_split_i (
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.clk (clk ),
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.rst (rst ),
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.i_tdata (i_axis.tdata ),
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.i_tuser (i_axis.tuser ),
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.i_tlast (i_axis.tlast ),
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.i_tvalid(i_axis.tvalid),
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.i_tready(i_axis.tready),
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.o_tdata (split_tdata ),
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.o_tuser (split_tuser ),
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.o_tlast (split_tlast ),
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.o_tvalid(split_tvalid ),
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.o_tready(split_tready )
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);
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axis_load_merge #(
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.IN_DATA_W (INT_DATA_W ),
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.IN_FIFO_SIZE (INT_WORD_FIFO_SIZE),
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.IN_NUM_PORTS (NUM_PORTS ),
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.OUT_DATA_W (DATA_W ),
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.OUT_FIFO_SIZE(EXT_FIFO_SIZE ),
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.USER_W (USER_W ),
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.USER_SEL (USER_SEL )
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) axis_load_merge_i (
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.clk (clk ),
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.rst (rst ),
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.i_tdata (split_tdata ),
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.i_tuser (masked_tuser ),
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.i_tlast (split_tlast ),
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.i_tvalid(split_tvalid ),
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.i_tready(split_tready ),
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.o_tdata (o_axis.tdata ),
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.o_tuser (o_axis.tuser ),
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.o_tlast (o_axis.tlast ),
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.o_tvalid(o_axis.tvalid),
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.o_tready(o_axis.tready)
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);
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//---------------------------------------------------------------------------
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// User Mask
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//---------------------------------------------------------------------------
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//
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// In order to verify that TUSER is used as expected, we mask the TUSER words
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// that should be ignored by axis_load_merge by changing them to X.
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//
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//---------------------------------------------------------------------------
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for (genvar port = 0; port < NUM_PORTS; port++) begin : gen_user_check
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int count;
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assign masked_tuser[port] = (count == USER_SEL) ? split_tuser[port] : 'X;
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always_ff @(posedge clk) begin
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if (split_tvalid[port] && split_tready[port]) begin
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if (split_tlast[port] || count == DATA_W/INT_DATA_W-1) begin
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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if (rst) begin
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count <= 0;
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end
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end
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end
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//---------------------------------------------------------------------------
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// Check Port Order
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//---------------------------------------------------------------------------
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//
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// Here we double check that the ports are used in a round robin order as
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// expected. This is done by checking the counter that's embedded in each
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// packet and making sure it corresponds to the correct port.
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//
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//---------------------------------------------------------------------------
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bit pkt_count_rst;
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for (genvar port = 0; port < NUM_PORTS; port++) begin : gen_port_check
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bit [PKT_COUNT_W-1:0] pkt_count = port;
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bit start_of_packet = 1;
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always_ff @(posedge clk) begin
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if (split_tvalid[port] && split_tready[port]) begin
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if (start_of_packet) begin
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`ASSERT_ERROR(
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split_tdata[port][0+:PKT_COUNT_W] == pkt_count,
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$sformatf(
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"Unexpected packet count on port %0d. Expected %0d, read %0d.",
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port, pkt_count, split_tdata[port]
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)
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);
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pkt_count <= pkt_count + NUM_PORTS;
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end
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start_of_packet <= split_tlast[port];
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end
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if (pkt_count_rst) begin
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pkt_count <= port;
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start_of_packet <= 1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// Test Procedures
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//---------------------------------------------------------------------------
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task automatic test_packets(int num_pkts = NUM_PKTS);
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pkt_t::data_t data_count = 0;
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mailbox pkt_mb = new();
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// Reset the packet counters
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clk_gen.clk_wait_f();
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pkt_count_rst <= 1;
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clk_gen.clk_wait_f();
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pkt_count_rst <= 0;
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fork
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begin : send_thread
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for (int pkt_count = 0; pkt_count < num_pkts; pkt_count++) begin
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pkt_t pkt;
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int pkt_length;
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logic [DATA_W-1:0] data;
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logic [USER_W-1:0] user;
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pkt = new();
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pkt_length = $urandom_range(1, MAX_PKT_LEN);
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repeat (pkt_length) begin
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data = USE_RANDOM ? Rand#(DATA_W)::rand_logic() : data_count;
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user = USE_RANDOM ? Rand#(DATA_W)::rand_logic() : ~data_count;
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pkt.data.push_back(data);
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pkt.user.push_back(user);
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data_count++;
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end
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// Put the packet count in the first byte of the packet so we can
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// easily tell the packets apart.
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pkt.data[0][0+:PKT_COUNT_W] = pkt_count;
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bfm.put(pkt);
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pkt_mb.put(pkt.copy());
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end
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end
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begin : recv_thread
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for (int pkt_count = 0; pkt_count < num_pkts; pkt_count++) begin
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pkt_t act_pkt, exp_pkt;
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bfm.get(act_pkt);
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act_pkt.keep = {}; // Not using keep, so remove the X's
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pkt_mb.get(exp_pkt);
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// Verify that we got the expected data
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`ASSERT_ERROR(
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exp_pkt.equal(act_pkt),
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$sformatf("On packet %0d, actual does not match expected", pkt_count)
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);
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end
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end
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join
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endtask : test_packets
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//---------------------------------------------------------------------------
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// Main
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//---------------------------------------------------------------------------
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initial begin : main
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string tb_name;
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// Generate a string for the name of this instance of the testbench
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tb_name = $sformatf({
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"rfnoc_block_fft_tb\n",
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"\tMAX_PKT_LEN = %0d\n",
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"\tDATA_W = %0d\n",
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"\tUSER_W = %0d\n",
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"\tUSER_SEL = %0d\n",
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"\tINT_DATA_W = %0d\n",
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"\tNUM_PORTS = %0d\n",
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"\tINT_FIFO_SIZE = %0d\n",
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"\tEXT_FIFO_SIZE = %0d"},
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MAX_PKT_LEN, DATA_W, USER_W, USER_SEL, INT_DATA_W, NUM_PORTS,
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INT_FIFO_SIZE, EXT_FIFO_SIZE
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);
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// Initialize the test exec object for this testbench
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test.start_tb(tb_name);
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// Start the clocks
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clk_gen.start();
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// Start the BFMs
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bfm.run();
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//--------------------------------
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// Reset
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//--------------------------------
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test.start_test("Reset");
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clk_gen.reset();
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@(negedge rst);
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test.end_test();
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//--------------------------------
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// Tests
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//--------------------------------
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test.start_test("Packet tests (normal)");
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bfm.set_slave_stall_prob(50);
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bfm.set_master_stall_prob(50);
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test_packets();
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test.end_test();
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test.start_test("Packet tests (back-pressure)");
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bfm.set_slave_stall_prob(95);
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bfm.set_master_stall_prob(5);
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test_packets();
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test.end_test();
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test.start_test("Packet tests (underflow)");
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bfm.set_slave_stall_prob(95);
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bfm.set_master_stall_prob(5);
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test_packets();
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test.end_test();
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//--------------------------------
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// Finish Up
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//--------------------------------
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// Display final statistics and results
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test.end_tb(0);
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// Kill the clocks to end this instance of the testbench
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clk_gen.kill();
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end
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endmodule
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