fpga: lib: Pipeline and add clken to ip_hdr_checksum

Adds LATENCY parameter to control the ammount of pieplineing. Adds a clock enable to control the advance of the pipeline. Used in xport when calculating new UDP headers for CHDR traffic. Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
2020-06-24 09:55:14 -05:00
parent 7b1174ffd9
commit b76ad2aef5
4 changed files with 51 additions and 66 deletions
@@ -324,8 +324,8 @@ module eth_ipv4_chdr64_adapter #(
  wire [15:0] udp_checksum = 16'h0;

  ip_hdr_checksum ip_hdr_checksum (
-    .clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0, my_ipv4_addr, ip_dst}),
-    .out(iphdr_checksum)
+    .clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0,
+    my_ipv4_addr, ip_dst}), .clken(1'b1), .out(iphdr_checksum)
  );

  always @(*) begin