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fpga: tools: Support new FPGA types in viv_simulator.mak

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This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.


Original-commit: 648c70ae758ab1d15c7ec6cbe57672e8c27640cd
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent 81e8b63fb9
commit b5230b0256
1 changed files with 2 additions and 2 deletions
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tools/make/viv_simulator.mak
+2 -2
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@@ -21,8 +21,8 @@ ifdef SIM_COMPLIBDIR
COMPLIBDIR = $(call RESOLVE_PATH,$(SIM_COMPLIBDIR))
endif
# Parse part name from ID
PART_NAME=$(subst /,,$(PART_ID))
# Get full part name, formatted for Vivado
PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(ARCH)/$(PART_ID)`
# Resolve path
EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS))