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fpga: tools: Disable common simulation warnings

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This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.


Original-commit: f094aa7ae0f864764276c5c67c51b21547327fb0
This commit is contained in:
Wade Fife
2025-03-17 13:40:26 -05:00
parent 6bcbd09a6b
commit b4943f4a61
1 changed files with 2 additions and 0 deletions
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tools/scripts/modelsim.do
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@@ -11,6 +11,8 @@
# #
quietly set BreakOnAssertion 2 quietly set BreakOnAssertion 2
quietly set StdArithNoWarnings 1
quietly set NumericStdNoWarnings 1
quietly set SIM_ERROR 0 quietly set SIM_ERROR 0
onbreak { onbreak {
quietly set FINISH [lindex [runStatus -full] 2] quietly set FINISH [lindex [runStatus -full] 2]