fpga: rfnoc: Add ULTRASCALE to chdr_ingress_fifo

Original-commit: a27d9e4fb92a895c0fe43b791e1d60838c8ad4c6

lib/rfnoc/core/chdr_ingress_fifo.v

@@ -26,6 +26,7 @@ module chdr_ingress_fifo #(
 );
 
   localparam SIZE_THRESHOLD = (
+    (DEVICE == "ULTRASCALE") ? 12 :  // Set to 12 to allow URAM
     (DEVICE == "7SERIES")    ? 14 : (
     (DEVICE == "VIRTEX6")    ? 14 : (
     (DEVICE == "SPARTAN6")   ? 12 : (
@@ -44,7 +45,7 @@ module chdr_ingress_fifo #(
   );
 
   generate
-    if (SIZE <= SIZE_THRESHOLD) begin
+    if (SIZE <= SIZE_THRESHOLD) begin : gen_single_fifo
       wire [WIDTH-1:0] o_tdata_int;
       wire             o_tlast_int, o_tvalid_int, o_tready_int;
       // Instantiate a single axi_fifo if size is not larger than threshold
@@ -60,7 +61,7 @@ module chdr_ingress_fifo #(
         .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
         .space(), .occupied()
       );
-    end else begin
+    end else begin : gen_fifo_cascade
       // Instantiate a cascade of axi_fifos if size is larger than threshold
       localparam CDEPTH = 2**(SIZE - SIZE_THRESHOLD); //Cascade Depth
       wire [WIDTH-1:0] c_tdata[CDEPTH:0], int_tdata[CDEPTH-1:0];
@@ -92,4 +93,4 @@ module chdr_ingress_fifo #(
     end
   endgenerate
 
-endmodule // axi_fifo_large
+endmodule // chdr_ingress_fifo