mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/x4xx_gpio_atr.v

@@ -14,14 +14,16 @@
 //
 // Parameters:
 //
-//   REG_BASE : Base address to use for registers.
-//   REG_SIZE : Register space size.
-//   WIDTH    : Number of GPIO lines controlled by this block.
+//   REG_BASE       : Base address to use for registers.
+//   REG_SIZE       : Register space size.
+//   WIDTH          : Number of GPIO lines controlled by this block.
+//   NUM_CH_PER_DB  : Number of RF Channels per daughterboard
 //
 module x4xx_gpio_atr #(
-  parameter REG_BASE = 0,
-  parameter REG_SIZE = 'h20,
-  parameter WIDTH    = 32
+  parameter REG_BASE      = 0,
+  parameter REG_SIZE      = 'h20,
+  parameter WIDTH         = 32,
+  parameter NUM_CH_PER_DB = 2
 ) (
   // Slave ctrlport interface
   input  wire        ctrlport_clk,
@@ -34,7 +36,7 @@ module x4xx_gpio_atr #(
   output reg  [ 1:0] s_ctrlport_resp_status = 2'b00,
   output reg  [31:0] s_ctrlport_resp_data   = {32 {1'bX}},
   // Run state signals that indicate tx and rx operation
-  input wire [3:0] db_state,
+  input wire [2*NUM_CH_PER_DB-1:0] db_state,
   // GPIO control signals
   input  wire [WIDTH-1:0]  gpio_in,                              //GPIO input state
   output reg  [WIDTH-1:0]  gpio_out  = {WIDTH {1'b0}},           //GPIO output state