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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/x4xx_global_regs.v
+20 -10
View File
@@ -55,7 +55,8 @@ module x4xx_global_regs #(
input wire pll_sync_done,
output reg [ 7:0] pps_brc_delay = 8'b0,
output reg [25:0] pps_prc_delay = 26'b0,
output reg [ 1:0] prc_rc_divider = 2'b0,
output reg [ 1:0] prc_rc0_divider = 2'b0,
output reg [ 1:0] prc_rc1_divider = 2'b0,
output reg pps_rc_enabled = 1'b0,
// Misc control and status signals (domain: s_ctrlport_clk)
@@ -77,7 +78,10 @@ module x4xx_global_regs #(
`include "../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/global_regs_regmap_utils.vh"
`include "regmap/versioning_regs_regmap_utils.vh"
// Variant-dependent register map.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
// Make DEVICE_ID default to anything but 0, since that has special meaning
localparam [DEVICE_ID_SIZE-1:0] DEFAULT_DEVICE_ID = 1;
@@ -191,7 +195,8 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY];
prc_rc_divider <= s_ctrlport_req_data[PRC_RC_DIVIDER_MSB:PRC_RC_DIVIDER];
prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER];
prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end
@@ -272,7 +277,8 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled;
s_ctrlport_resp_data[PRC_RC_DIVIDER_MSB:PRC_RC_DIVIDER] <= prc_rc_divider;
s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider;
s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end
@@ -576,9 +582,16 @@ endmodule
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC_DIVIDER" range="29..28">
// <bitfield name="PRC_RC1_DIVIDER" range="27..26">
// <info>
// Clock multiplier used to generate radio clock from PLL reference clock.
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="29..28">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
@@ -596,10 +609,7 @@ endmodule
// </register>
// <register name="CHDR_CLK_RATE_REG" offset="0x20" size="32" writable="false">
// <info>Returns the RFNoC bus clock rate (CHDR).</info>
// <bitfield name="CHDR_CLK" range="31..0" initialvalue="CHDR_CLK_VALUE">
// <enumeratedtype name="CHDR_CLK_ENUM" showhex="true">
// <value name="CHDR_CLK_VALUE" integer="200000000"/>
// </enumeratedtype>
// <bitfield name="CHDR_CLK" range="31..0">
// </bitfield>
// </register>
// <register name="CHDR_CLK_COUNT_REG" offset="0x24" size="32" writable="false">