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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/x4xx_core_common.v
+171 -146
View File
@@ -14,32 +14,36 @@
// the ctrlport interfaces in the radios, or a mix of both. A visual
// representation of how the AXI Ctrlport interface and the
// Ctrlport of each radio interact with the different blocks in this module
// can be found in ./doc/x4xx_core_common_buses.svg
// can be found in ./doc/common/x4xx_core_common_buses.svg
//
// Parameters:
//
// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
// CHDR_W : CHDR protocol width
// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
// Minor is least significant byte)
// NUM_DBOARDS : Number of daughter boards to support
// PCIE_PRESENT : Indicates if PCIe is present in this image
// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
// CHDR_W : CHDR protocol width
// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
// Minor is least significant byte)
// NUM_DBOARDS : Number of daughter boards to support
// NUM_CH_PER_DB : Number of RF Channels per daughterboard
// NUM_TIMEKEEPERS : Number of timekeepers
// PCIE_PRESENT : Indicates if PCIe is present in this image
//
`default_nettype none
module x4xx_core_common #(
parameter CHDR_CLK_RATE = 200000000,
parameter CHDR_W = 64,
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NUM_DBOARDS = 2,
parameter PCIE_PRESENT = 0
parameter CHDR_CLK_RATE = 200000000,
parameter CHDR_W = 64,
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NUM_DBOARDS = 2,
parameter NUM_CH_PER_DB = 2,
parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
parameter PCIE_PRESENT = 0
) (
// Clocks and resets
input wire radio_clk,
input wire radio_clk_2x,
input wire radio_rst,
input wire [NUM_DBOARDS-1:0] radio_clk,
input wire [NUM_DBOARDS-1:0] radio_clk_2x,
input wire [NUM_DBOARDS-1:0] radio_rst,
input wire rfnoc_chdr_clk,
input wire rfnoc_chdr_rst,
@@ -65,7 +69,7 @@ module x4xx_core_common #(
output wire [31:0] s_ctrlport_resp_data,
// PPS (top-level inputs)
input wire pps_radioclk,
input wire [ 1:0] pps_radioclk,
// PPS and clock control (Domain: rfnoc_ctrl_clk)
output wire [ 1:0] pps_select,
@@ -75,14 +79,15 @@ module x4xx_core_common #(
input wire pll_sync_done,
output wire [ 7:0] pps_brc_delay,
output wire [25:0] pps_prc_delay,
output wire [ 1:0] prc_rc_divider,
output wire [ 1:0] prc_rc0_divider,
output wire [ 1:0] prc_rc1_divider,
output wire pps_rc_enabled,
// Timekeeper (Domain: radio_clk)
input wire [ 7:0] radio_spc,
output wire [63:0] radio_time,
input wire sample_rx_stb,
input wire [ 3:0] time_ignore_bits,
input wire [ 7:0] radio_spc,
input wire sample_rx_stb,
input wire [ 3:0] time_ignore_bits,
output wire [64*NUM_TIMEKEEPERS-1:0] radio_time,
// GPIO to DIO board (Domain: radio_clk)
output wire [11:0] gpio_en_a,
@@ -135,8 +140,8 @@ module x4xx_core_common #(
output wire dac_reset_pulse,
// Radio state for ATR control
input wire [NUM_DBOARDS*2-1:0] tx_running,
input wire [NUM_DBOARDS*2-1:0] rx_running,
input wire [NUM_DBOARDS*NUM_CH_PER_DB-1:0] tx_running,
input wire [NUM_DBOARDS*NUM_CH_PER_DB-1:0] rx_running,
// Misc (Domain: rfnoc_ctrl_clk)
input wire [31:0] qsfp_port_0_0_info,
@@ -177,13 +182,22 @@ module x4xx_core_common #(
wire [CTRLPORT_DATA_W-1:0] m_resp_data;
// Split ctrlport for multiple endpoints (domain: rfnoc_ctrl_clk)
wire timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr;
wire timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd;
wire [CTRLPORT_ADDR_W-1:0] timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr;
wire [CTRLPORT_DATA_W-1:0] timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data;
wire timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
wire [ CTRLPORT_STS_W-1:0] timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status;
wire [CTRLPORT_DATA_W-1:0] timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data;
wire versioning_req_wr, global_regs_req_wr, dio_req_wr;
wire versioning_req_rd, global_regs_req_rd, dio_req_rd;
wire [CTRLPORT_ADDR_W-1:0] versioning_req_addr, global_regs_req_addr, dio_req_addr;
wire [CTRLPORT_DATA_W-1:0] versioning_req_data, global_regs_req_data, dio_req_data;
wire versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
wire [ CTRLPORT_STS_W-1:0] versioning_resp_status, global_regs_resp_status, dio_resp_status;
wire [CTRLPORT_DATA_W-1:0] versioning_resp_data, global_regs_resp_data, dio_resp_data;
// Timekeeper ctrlports
wire [NUM_TIMEKEEPERS-1:0] timekeeper_req_wr;
wire [NUM_TIMEKEEPERS-1:0] timekeeper_req_rd;
wire [NUM_TIMEKEEPERS*CTRLPORT_ADDR_W-1:0] timekeeper_req_addr;
wire [NUM_TIMEKEEPERS*CTRLPORT_DATA_W-1:0] timekeeper_req_data;
wire [NUM_TIMEKEEPERS-1:0] timekeeper_resp_ack;
wire [NUM_TIMEKEEPERS*CTRLPORT_DATA_W-1:0] timekeeper_resp_data;
wire [NUM_TIMEKEEPERS*CTRLPORT_STS_W-1:0] timekeeper_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_i (
.rst (ctrlport_rst),
@@ -218,7 +232,7 @@ module x4xx_core_common #(
);
ctrlport_splitter #(
.NUM_SLAVES (4)
.NUM_SLAVES (3+NUM_TIMEKEEPERS)
) ctrlport_splitter_i (
.ctrlport_clk (rfnoc_ctrl_clk),
.ctrlport_rst (rfnoc_ctrl_rst),
@@ -249,8 +263,6 @@ module x4xx_core_common #(
// Global Registers
// -------------------------------------------------------------------
localparam NUM_TIMEKEEPERS = 1;
x4xx_global_regs #(
.REG_BASE (GLOBAL_REGS),
.REG_SIZE (GLOBAL_REGS_SIZE),
@@ -278,7 +290,8 @@ module x4xx_core_common #(
.pll_sync_done (pll_sync_done),
.pps_brc_delay (pps_brc_delay),
.pps_prc_delay (pps_prc_delay),
.prc_rc_divider (prc_rc_divider),
.prc_rc0_divider (prc_rc0_divider),
.prc_rc1_divider (prc_rc1_divider),
.pps_rc_enabled (pps_rc_enabled),
.qsfp_port_0_0_info (qsfp_port_0_0_info),
.qsfp_port_0_1_info (qsfp_port_0_1_info),
@@ -319,29 +332,34 @@ module x4xx_core_common #(
// Timekeeper
//---------------------------------------------------------------------------
assign timekeeper_resp_status = CTRL_STS_OKAY;
assign timekeeper_resp_status = {NUM_TIMEKEEPERS{CTRL_STS_OKAY}};
localparam TIMEKEEPERS = {TIMEKEEPER_B[CTRLPORT_ADDR_W-1:0], TIMEKEEPER_A[CTRLPORT_ADDR_W-1:0]};
timekeeper #(
.BASE_ADDR (TIMEKEEPER),
.TIME_INCREMENT (0)
) timekeeper_i (
.tb_clk (radio_clk),
.tb_rst (radio_rst),
.s_ctrlport_clk (rfnoc_ctrl_clk),
.s_ctrlport_req_wr (timekeeper_req_wr),
.s_ctrlport_req_rd (timekeeper_req_rd),
.s_ctrlport_req_addr (timekeeper_req_addr),
.s_ctrlport_req_data (timekeeper_req_data),
.s_ctrlport_resp_ack (timekeeper_resp_ack),
.s_ctrlport_resp_data (timekeeper_resp_data),
.time_increment (radio_spc),
.sample_rx_stb (sample_rx_stb),
.pps (pps_radioclk),
.tb_timestamp (radio_time),
.tb_timestamp_last_pps (),
.tb_period_ns_q32 (),
.tb_changed ()
);
genvar tk_i;
generate
for (tk_i = 0; tk_i < NUM_TIMEKEEPERS; tk_i = tk_i+1) begin : gen_timekeeper
timekeeper #(
.BASE_ADDR (TIMEKEEPERS[CTRLPORT_ADDR_W*tk_i+:CTRLPORT_ADDR_W]),
.TIME_INCREMENT (0)
) timekeeper_i (
.tb_clk (radio_clk[tk_i]),
.tb_rst (radio_rst[tk_i]),
.s_ctrlport_clk (rfnoc_ctrl_clk),
.s_ctrlport_req_wr (timekeeper_req_wr[tk_i]),
.s_ctrlport_req_rd (timekeeper_req_rd[tk_i]),
.s_ctrlport_req_addr (timekeeper_req_addr[CTRLPORT_ADDR_W*tk_i+:CTRLPORT_ADDR_W]),
.s_ctrlport_req_data (timekeeper_req_data[CTRLPORT_DATA_W*tk_i+:CTRLPORT_DATA_W]),
.s_ctrlport_resp_ack (timekeeper_resp_ack[tk_i]),
.s_ctrlport_resp_data (timekeeper_resp_data[CTRLPORT_DATA_W*tk_i+:CTRLPORT_DATA_W]),
.time_increment (radio_spc),
.sample_rx_stb (sample_rx_stb),
.pps (pps_radioclk[tk_i]),
.tb_timestamp (radio_time[64*tk_i+:64]),
.tb_timestamp_last_pps (),
.tb_period_ns_q32 ()
);
end
endgenerate
//-----------------------------------------------------------------------
@@ -389,9 +407,9 @@ module x4xx_core_common #(
wire [NUM_DBOARDS*32-1:0] spi_gpio_out;
wire [NUM_DBOARDS*32-1:0] spi_gpio_ddr;
genvar db;
genvar db_i, ch_i;
generate
for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport
for ( db_i = 0; db_i < NUM_DBOARDS; db_i = db_i + 1) begin : gen_radio_ctrlport
//----------------------------------------------------------------------------
// Timed command processing
@@ -408,21 +426,23 @@ module x4xx_core_common #(
ctrlport_timer #(
.EXEC_LATE_CMDS(1)
) ctrlport_timer_i (
.clk (radio_clk),
.rst (radio_rst),
.clk (radio_clk[db_i]),
.rst (radio_rst[db_i]),
`ifdef X410
.time_now (radio_time),
`endif
.time_now_stb (sample_rx_stb),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db+:32]),
.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db+: 4]),
.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db+: 1]),
.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db+:64]),
.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]),
.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db_i+: 4]),
.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db_i+: 1]),
.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db_i+:64]),
.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db_i+:32]),
.m_ctrlport_req_wr (ctrlport_timed_req_wr),
.m_ctrlport_req_rd (ctrlport_timed_req_rd),
.m_ctrlport_req_addr (ctrlport_timed_req_addr),
@@ -440,7 +460,7 @@ module x4xx_core_common #(
// This section takes the CtrlPort master from each radio block and splits it
// into a CtrlPort bus for the associated daughter(m_radio_ctrlport_*), the
// RFDC timing control (rf_ctrlport_*), the ATR GPIO control for the DB state
// the current radio(db), the SPI controller of the radio, and DIO main
// the current radio(db_i), the SPI controller of the radio, and DIO main
// control block(x4xx_dio).
// Refer to diagram in the RADIO_CTRLPORT_REGMAP Register map for a
// visual representation on how these interfaces are distributed.
@@ -472,8 +492,8 @@ module x4xx_core_common #(
DB_WINDOW_SIZE_W
})
) ctrlport_decoder_param_i (
.ctrlport_clk ( radio_clk ),
.ctrlport_rst ( radio_rst ),
.ctrlport_clk ( radio_clk[db_i] ),
.ctrlport_rst ( radio_rst[db_i] ),
.s_ctrlport_req_wr ( ctrlport_timed_req_wr),
.s_ctrlport_req_rd ( ctrlport_timed_req_rd),
.s_ctrlport_req_addr ( ctrlport_timed_req_addr),
@@ -484,85 +504,87 @@ module x4xx_core_common #(
.s_ctrlport_resp_ack ( ctrlport_timed_resp_ack),
.s_ctrlport_resp_status ( ctrlport_timed_resp_status),
.s_ctrlport_resp_data ( ctrlport_timed_resp_data),
.m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db+: 1],
radio_dio_req_wr [ 1*db+: 1],
gpio_atr_ctrlport_req_wr [ 1*db+: 1],
rf_ctrlport_req_wr [ 1*db+: 1],
m_radio_ctrlport_req_wr [ 1*db+: 1] }),
.m_ctrlport_req_rd ({ gpio_spi_ctrlport_req_rd [ 1*db+: 1],
radio_dio_req_rd [ 1*db+: 1],
gpio_atr_ctrlport_req_rd [ 1*db+: 1],
rf_ctrlport_req_rd [ 1*db+: 1],
m_radio_ctrlport_req_rd [ 1*db+: 1] }),
.m_ctrlport_req_addr ({ gpio_spi_ctrlport_req_addr [20*db+:20],
radio_dio_req_addr [20*db+:20],
gpio_atr_ctrlport_req_addr [20*db+:20],
rf_ctrlport_req_addr [20*db+:20],
m_radio_ctrlport_req_addr [20*db+:20] }),
.m_ctrlport_req_data ({ gpio_spi_ctrlport_req_data [32*db+:32],
radio_dio_req_data [32*db+:32],
gpio_atr_ctrlport_req_data [32*db+:32],
rf_ctrlport_req_data [32*db+:32],
m_radio_ctrlport_req_data [32*db+:32] }),
.m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db_i+: 1],
radio_dio_req_wr [ 1*db_i+: 1],
gpio_atr_ctrlport_req_wr [ 1*db_i+: 1],
rf_ctrlport_req_wr [ 1*db_i+: 1],
m_radio_ctrlport_req_wr [ 1*db_i+: 1] }),
.m_ctrlport_req_rd ({ gpio_spi_ctrlport_req_rd [ 1*db_i+: 1],
radio_dio_req_rd [ 1*db_i+: 1],
gpio_atr_ctrlport_req_rd [ 1*db_i+: 1],
rf_ctrlport_req_rd [ 1*db_i+: 1],
m_radio_ctrlport_req_rd [ 1*db_i+: 1] }),
.m_ctrlport_req_addr ({ gpio_spi_ctrlport_req_addr [20*db_i+:20],
radio_dio_req_addr [20*db_i+:20],
gpio_atr_ctrlport_req_addr [20*db_i+:20],
rf_ctrlport_req_addr [20*db_i+:20],
m_radio_ctrlport_req_addr [20*db_i+:20] }),
.m_ctrlport_req_data ({ gpio_spi_ctrlport_req_data [32*db_i+:32],
radio_dio_req_data [32*db_i+:32],
gpio_atr_ctrlport_req_data [32*db_i+:32],
rf_ctrlport_req_data [32*db_i+:32],
m_radio_ctrlport_req_data [32*db_i+:32] }),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db+: 1],
radio_dio_resp_ack [ 1*db+: 1],
gpio_atr_ctrlport_resp_ack [ 1*db+: 1],
rf_ctrlport_resp_ack [ 1*db+: 1],
m_radio_ctrlport_resp_ack [ 1*db+: 1] }),
.m_ctrlport_resp_status ({ gpio_spi_ctrlport_resp_status [ 2*db+: 2],
radio_dio_resp_status [ 2*db+: 2],
gpio_atr_ctrlport_resp_status [ 2*db+: 2],
rf_ctrlport_resp_status [ 2*db+: 2],
m_radio_ctrlport_resp_status [ 2*db+: 2] }),
.m_ctrlport_resp_data ({ gpio_spi_ctrlport_resp_data [32*db+:32],
radio_dio_resp_data [32*db+:32],
gpio_atr_ctrlport_resp_data [32*db+:32],
rf_ctrlport_resp_data [32*db+:32],
m_radio_ctrlport_resp_data [32*db+:32] })
.m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db_i+: 1],
radio_dio_resp_ack [ 1*db_i+: 1],
gpio_atr_ctrlport_resp_ack [ 1*db_i+: 1],
rf_ctrlport_resp_ack [ 1*db_i+: 1],
m_radio_ctrlport_resp_ack [ 1*db_i+: 1] }),
.m_ctrlport_resp_status ({ gpio_spi_ctrlport_resp_status [ 2*db_i+: 2],
radio_dio_resp_status [ 2*db_i+: 2],
gpio_atr_ctrlport_resp_status [ 2*db_i+: 2],
rf_ctrlport_resp_status [ 2*db_i+: 2],
m_radio_ctrlport_resp_status [ 2*db_i+: 2] }),
.m_ctrlport_resp_data ({ gpio_spi_ctrlport_resp_data [32*db_i+:32],
radio_dio_resp_data [32*db_i+:32],
gpio_atr_ctrlport_resp_data [32*db_i+:32],
rf_ctrlport_resp_data [32*db_i+:32],
m_radio_ctrlport_resp_data [32*db_i+:32] })
);
// Compute ATR state for this radio
wire [ 3:0] db_state;
wire [ 2*NUM_CH_PER_DB-1:0] db_state;
assign db_state = { tx_running[2*db + 1], rx_running[2*db + 1],
tx_running[2*db + 0], rx_running[2*db + 0]};
for ( ch_i = 0; ch_i < NUM_CH_PER_DB; ch_i = ch_i + 1) begin: gen_db_state_ch
assign db_state[ch_i*2] = rx_running[NUM_CH_PER_DB*db_i+ch_i];
assign db_state[ch_i*2+1] = tx_running[NUM_CH_PER_DB*db_i+ch_i];
end
x4xx_gpio_atr #(
.REG_SIZE (RADIO_GPIO_ATR_REGS_SIZE)
) x4xx_gpio_atr_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (gpio_atr_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (gpio_atr_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (gpio_atr_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (gpio_atr_ctrlport_req_data [32*db+:32]),
.s_ctrlport_resp_ack (gpio_atr_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (gpio_atr_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (gpio_atr_ctrlport_resp_data [32*db+:32]),
.ctrlport_clk (radio_clk[db_i]),
.ctrlport_rst (radio_rst[db_i]),
.s_ctrlport_req_wr (gpio_atr_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (gpio_atr_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (gpio_atr_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (gpio_atr_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_resp_ack (gpio_atr_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (gpio_atr_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (gpio_atr_ctrlport_resp_data [32*db_i+:32]),
.db_state (db_state),
.gpio_in ({4'b0, gpio_in_b, 4'b0, gpio_in_a}),
.gpio_out (atr_gpio_out[db*32+: 32]),
.gpio_ddr (atr_gpio_ddr[db*32+: 32])
.gpio_out (atr_gpio_out[db_i*32+: 32]),
.gpio_ddr (atr_gpio_ddr[db_i*32+: 32])
);
x4xx_gpio_spi #(
.NUM_SLAVES (2)
) x4xx_gpio_spi_i(
.ctrlport_clk (radio_clk),
.ctrlport_clk_2x (radio_clk_2x),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (gpio_spi_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (gpio_spi_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (gpio_spi_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (gpio_spi_ctrlport_req_data [32*db+:32]),
.s_ctrlport_resp_ack (gpio_spi_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (gpio_spi_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (gpio_spi_ctrlport_resp_data [32*db+:32]),
.gpio_out (spi_gpio_out[db*32+: 32]),
.gpio_ddr (spi_gpio_ddr[db*32+: 32]),
.ctrlport_clk (radio_clk[db_i]),
.ctrlport_clk_2x (radio_clk_2x[db_i]),
.ctrlport_rst (radio_rst[db_i]),
.s_ctrlport_req_wr (gpio_spi_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (gpio_spi_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (gpio_spi_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (gpio_spi_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_resp_ack (gpio_spi_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (gpio_spi_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (gpio_spi_ctrlport_resp_data [32*db_i+:32]),
.gpio_out (spi_gpio_out[db_i*32+: 32]),
.gpio_ddr (spi_gpio_ddr[db_i*32+: 32]),
.gpio_in ({4'b0, gpio_in_b, 4'b0, gpio_in_a})
);
@@ -577,8 +599,8 @@ module x4xx_core_common #(
rfdc_timing_control #(
.NUM_DBOARDS (NUM_DBOARDS)
) rfdc_timing_control_i (
.clk (radio_clk),
.rst (radio_rst),
.clk (radio_clk[0]),
.rst (radio_rst[0]),
.s_ctrlport_req_wr (rf_ctrlport_req_wr),
.s_ctrlport_req_rd (rf_ctrlport_req_rd),
.s_ctrlport_req_addr (rf_ctrlport_req_addr),
@@ -641,7 +663,7 @@ module x4xx_core_common #(
.s_ctrlport_resp_ack (dio_resp_ack),
.s_ctrlport_resp_status (dio_resp_status),
.s_ctrlport_resp_data (dio_resp_data),
.m_ctrlport_clk (radio_clk),
.m_ctrlport_clk (radio_clk[0]),
.m_ctrlport_req_wr (mpm_dio_req_wr),
.m_ctrlport_req_rd (mpm_dio_req_rd),
.m_ctrlport_req_addr (mpm_dio_req_addr),
@@ -680,8 +702,8 @@ module x4xx_core_common #(
.PORT_BASE ({DIO[19:0]}),
.PORT_ADDR_W ({$clog2(DIO_SIZE)})
) ctrlport_decoder_dio_window (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr (mpm_dio_req_wr),
.s_ctrlport_req_rd (mpm_dio_req_rd),
.s_ctrlport_req_addr (mpm_dio_req_addr),
@@ -721,8 +743,8 @@ module x4xx_core_common #(
.NUM_MASTERS (NUM_DBOARDS + 1),
.PRIORITY (1)
) ctrlport_combiner_dio (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr ({radio_dio_req_wr, windowed_mpm_dio_req_wr}),
.s_ctrlport_req_rd ({radio_dio_req_rd, windowed_mpm_dio_req_rd}),
.s_ctrlport_req_addr ({radio_dio_req_addr, windowed_mpm_dio_req_addr}),
@@ -755,8 +777,8 @@ module x4xx_core_common #(
.REG_SIZE (DIO_SIZE),
.NUM_DBOARDS (NUM_DBOARDS)
) x4xx_dio_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr (dio_ctrlport_req_wr),
.s_ctrlport_req_rd (dio_ctrlport_req_rd),
.s_ctrlport_req_addr (dio_ctrlport_req_addr),
@@ -802,7 +824,7 @@ endmodule
// starts at offset 0x80000 in the RFNoC Radio block's register space.
// The following diagram displays the distribution of the CtrlPort
// interface to the different modules it interacts with.
// <img src = "x4xx_core_common_buses.svg"
// <img src = "../common/x4xx_core_common_buses.svg"
// </info>
// <window name="DB_WINDOW" offset="0x00000" size="0x08000">
// <info>Daughterboard GPIO interface. Register access within this space
@@ -829,7 +851,7 @@ endmodule
//
// The following diagram shows how the communication bus interacts with the
// modules in CORE_REGS.
// <img src = "x4xx_core_common_buses.svg"
// <img src = "../common/x4xx_core_common_buses.svg"
// </info>
// <group name="CORE_REGS">
// <window name="GLOBAL_REGS" offset="0x0" size="0xC00" targetregmap="GLOBAL_REGS_REGMAP">
@@ -838,7 +860,10 @@ endmodule
// <window name="VERSIONING_REGS" offset="0xC00" size="0x400" targetregmap="VERSIONING_REGS_REGMAP">
// <info>Window to access versioning registers in the FPGA.</info>
// </window>
// <window name="TIMEKEEPER" offset="0x1000" size="0x20">
// <window name="TIMEKEEPER_A" offset="0x1000" size="0x20">
// <info>Window to access the timekeeper register map.</info>
// </window>
// <window name="TIMEKEEPER_B" offset="0x1100" size="0x20">
// <info>Window to access the timekeeper register map.</info>
// </window>
// <window name="DIO" offset="0x2000" size="0x40" targetregmap="DIO_REGMAP">