mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
@@ -0,0 +1,300 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: x410_clock_gates
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--
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-- Description:
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--
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-- Gate propagation of DataClk and RfdcClk instances until the PLL lock
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-- status signal is stable and software has acknowledged it by asserting the
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-- pertinent controls.
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--
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-- RfdcClks are used on other Xilinx IP components in the Board Design, and
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-- Vivado fails to detect their frequency correctly their buffer is
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-- explicitly instantiated in the Block Design. Therefore, we only generate
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-- the buffer enable signals for these clocks within this component.
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--
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-- Since DataClk are only used in other Custom IP blocks within the Block
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-- design, it is possible to instantiate the clock buffers within this block
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-- for without running into IP generation failures.
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--
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-- Parameters:
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--
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-- kReliableClkPeriodNs: Clock period (ns) for ReliableClk.
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--
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity x410_clock_gates is
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generic (
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kReliableClkPeriodNs : integer := 25
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);
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port (
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-- MMCM reset
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-- This clock will be asserted via AXI access before any clocking
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-- configuration done, signals coming into this component will not change
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-- immediately after this reset is de-asserted.
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rPllReset_n : in std_logic;
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aPllLocked : in std_logic;
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-- Input Clocks (from MMCM)
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ReliableClk : in std_logic;
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DataClk1xPll : in std_logic;
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DataClk2xPll : in std_logic;
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-- Buffered Clock Outputs (to design)
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DataClk1x : out std_logic;
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DataClk2x : out std_logic;
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-- Buffers for these signals must be instantiated on Block design for clock
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-- rates to be identified. The Utility Buffers instantiated on the Block
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-- Design require signals to be of type std_logic_vector.
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aEnableRfBufg1x : out std_logic_vector(0 downto 0);
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aEnableRfBufg2x : out std_logic_vector(0 downto 0);
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-- PLL Status Signals
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rPllLocked : out std_logic;
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-- Window Interface
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rSafeToEnableGatedClks : in std_logic;
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rGatedBaseClksValid : out std_logic;
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-- AXI GPIO interface
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rSoftwareControl : in std_logic_vector(31 downto 0);
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rSoftwareStatus : out std_logic_vector(31 downto 0)
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);
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end x410_clock_gates;
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architecture STRUCT of x410_clock_gates is
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component sync_wrapper
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generic (
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WIDTH : integer := 1;
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STAGES : integer := 2;
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INITIAL_VAL : integer := 0;
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FALSE_PATH_TO_IN : integer := 1);
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port (
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clk : in std_logic;
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rst : in std_logic;
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signal_in : in std_logic_vector((WIDTH-1) downto 0);
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signal_out : out std_logic_vector((WIDTH-1) downto 0));
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end component;
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component BUFGCE
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generic(
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CE_TYPE : string);
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port (
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O : out std_ulogic;
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CE : in std_ulogic;
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I : in std_ulogic);
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end component;
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-- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the
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-- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an
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-- integer, Vivado could either round up or down. In case they round down, we
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-- add '1' to the result to ensure we have the full lock time accounted for.
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-- In this case, it is better to count 1 more than necessary than kill the
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-- process prematurely.
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constant kPllLockTimeNs : integer := 100000;
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constant kMaxPllLockCount : integer := kPllLockTimeNs / kReliableClkPeriodNs + 1;
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signal rLockedFilterCount : integer range 0 to kMaxPllLockCount-1 := kMaxPllLockCount-1;
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signal rClearDataClkUnlockedSticky : std_logic;
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-----------------------------------------------------------------------------
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-- PLL locked signals
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-----------------------------------------------------------------------------
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-- Synchronizer signals
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signal aPllLockedLcl : std_logic_vector(0 downto 0);
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signal rPllLockedDs : std_logic_vector(0 downto 0) := (others => '0');
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-- Lock status indicators
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signal rPllLockedLcl : std_logic := '0';
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signal rPllUnlockedSticky : std_logic := '0';
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-- Safe BUFG enable signals
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signal rEnableDataClk1x,
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rEnableDataClk2x,
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rEnableRfdcClk1x,
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rEnableRfdcClk2x : std_logic;
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signal rEnableDataBufg1x : std_logic := '0';
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signal rEnableDataBufg2x : std_logic := '0';
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signal rEnableRfdcBufg1xLcl : std_logic := '0';
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signal rEnableRfdcBufg2xLcl : std_logic := '0';
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-- Active high version of reset required for synchronizer blocks.
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signal rPllReset : std_logic;
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-- Since these signals control sensitive components (clock enables), we apply
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-- a dont_touch attribute to preserve the signals through both synthesis and
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-- P&R. Implementation of "dont_touch" has been confirmed after P&R.
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attribute dont_touch : string;
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attribute dont_touch of rEnableDataBufg1x : signal is "TRUE";
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attribute dont_touch of rEnableDataBufg2x : signal is "TRUE";
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attribute dont_touch of aEnableRfBufg1x : signal is "TRUE";
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attribute dont_touch of aEnableRfBufg2x : signal is "TRUE";
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attribute X_INTERFACE_INFO : string;
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attribute X_INTERFACE_PARAMETER : string;
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attribute X_INTERFACE_INFO of DataClk1xPll : signal is
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"xilinx.com:signal:clock:1.0 DataClk1xPll CLK";
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attribute X_INTERFACE_INFO of DataClk2xPll : signal is
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"xilinx.com:signal:clock:1.0 DataClk2xPll CLK";
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begin
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rPllReset <= not rPllReset_n;
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-- Assert rGatedBaseClksValid once the PLL has been locked for the specified
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-- time.
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rGatedBaseClksValid <= rPllLockedLcl;
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DataClkEnables : process(ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rEnableDataBufg1x <= '0';
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rEnableDataBufg2x <= '0';
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rEnableRfdcBufg1xLcl <= '0';
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rEnableRfdcBufg2xLcl <= '0';
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else
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rEnableDataBufg1x <=
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rSafeToEnableGatedClks and
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rEnableDataClk1x and
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(not rPllUnlockedSticky);
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rEnableDataBufg2x <=
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rSafeToEnableGatedClks and
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rEnableDataClk2x and
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(not rPllUnlockedSticky);
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rEnableRfdcBufg1xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdcClk1x and
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(not rPllUnlockedSticky);
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rEnableRfdcBufg2xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdcClk2x and
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(not rPllUnlockedSticky);
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end if;
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end if;
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end process DataClkEnables;
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aEnableRfBufg1x(0) <= rEnableRfdcBufg1xLcl;
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aEnableRfBufg2x(0) <= rEnableRfdcBufg2xLcl;
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DataClk1xSafeBufg: BUFGCE
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generic map(
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CE_TYPE => "ASYNC"
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)
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port map (
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I => DataClk1xPll,
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CE => rEnableDataBufg1x,
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O => DataClk1x
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);
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DataClk2xSafeBufg: BUFGCE
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generic map(
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CE_TYPE => "ASYNC"
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)
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port map (
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I => DataClk2xPll,
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CE => rEnableDataBufg2x,
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O => DataClk2x
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);
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-----------------------------------------------------------------------------
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-- Create PLL Lock Signal
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-----------------------------------------------------------------------------
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-- Double-sync the incoming aPllLocked signal from the PLL.
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aPllLockedLcl(0) <= aPllLocked;
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DataClkPllLockedDS: sync_wrapper
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generic map (
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WIDTH => 1,
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STAGES => open,
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INITIAL_VAL => open,
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FALSE_PATH_TO_IN => open)
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port map (
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clk => ReliableClk,
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rst => rPllReset,
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signal_in => aPllLockedLcl,
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signal_out => rPllLockedDs
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);
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-- Filter the Lock signal. Assert a lock when the PLL lock signal has been
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-- asserted for kPllLockTimeNs
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--
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-- !!! SAFE COUNTER STARTUP !!!
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-- rLockedFilterCount cannot start incrementing until rPllReset_n is
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-- de-asserted. Once rPllReset_n is de-asserted through a AXI access, input
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-- values for the registers in this state machine will not change until the
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-- MMCM locks and the double synchronizer reflects a locked status, making
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-- this start-up safe.
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PllLockFilter: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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else
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if rPllLockedDs(0) = '1' then
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if rLockedFilterCount = 0 then
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rPllLockedLcl <= '1';
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else
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rPllLockedLcl <= '0';
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rLockedFilterCount <= rLockedFilterCount - 1;
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end if;
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else
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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end if;
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end if;
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end if;
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end process PllLockFilter;
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-- Sticky bit to hold '1' if PLL ever comes unlocked
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PllStickyBit: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if (not rPllReset_n or rClearDataClkUnlockedSticky) = '1' then
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rPllUnlockedSticky <= '0';
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else
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if rPllLockedLcl = '1' and rPllLockedDs(0) = '0' then
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rPllUnlockedSticky <= '1';
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end if;
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end if;
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end if;
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end process;
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rPllLocked <= rPllLockedLcl;
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-- AXI transaction decoding
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rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
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rEnableDataClk1x <= rSoftwareControl(kENABLE_DATA_CLK);
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rEnableDataClk2x <= rSoftwareControl(kENABLE_DATA_CLK_2X);
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rEnableRfdcClk1x <= rSoftwareControl(kENABLE_RF_CLK);
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rEnableRfdcClk2x <= rSoftwareControl(kENABLE_RF_CLK_2X);
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rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl;
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rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky;
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end STRUCT;
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@@ -0,0 +1,208 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: x410_rf_reset_controller
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--
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-- Description:
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--
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-- Control RFDC, ADC, and DAC resets.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity x410_rf_reset_controller is
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port(
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-- Clocks
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-- Config clock is async to all the others.
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ConfigClk : in std_logic;
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DataClk : in std_logic;
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PllRefClk : in std_logic;
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RfClk : in std_logic;
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RfClk2x : in std_logic;
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DataClk2x : in std_logic;
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-- Master resets from the Radio
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dAdcResetPulse : in std_logic;
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dDacResetPulse : in std_logic;
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-- ADC Resets
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dAdcDataOutReset_n : out std_logic;
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r2AdcFirReset_n : out std_logic;
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rAdcRfdcAxiReset_n : out std_logic;
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rAdcEnableData : out std_logic;
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rAdcGearboxReset_n : out std_logic;
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-- DAC Resets
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dDacDataInReset_n : out std_logic;
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r2DacFirReset_n : out std_logic;
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d2DacFirReset_n : out std_logic;
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rDacRfdcAxiReset_n : out std_logic;
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rDacGearboxReset_n : out std_logic;
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-- SW Control and Status
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-- Control to initiate resets to RFDC and decimation block including the
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-- gearboxes. The reset status is a sticky status of both ADC and DAC.
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cSoftwareControl : in std_logic_vector(31 downto 0);
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cSoftwareStatus : out std_logic_vector(31 downto 0)
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);
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end x410_rf_reset_controller;
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architecture RTL of x410_rf_reset_controller is
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-- POR value for all resets are high.
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signal cTriggerAdcReset : std_logic := '1';
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signal cTriggerAdcResetDlyd : std_logic := '1';
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signal cTriggerDacReset : std_logic := '1';
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signal cTriggerDacResetDlyd : std_logic := '1';
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signal dTriggerAdcReset_ms : std_logic := '1';
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signal dTriggerAdcReset : std_logic := '1';
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signal dTriggerDacReset_ms : std_logic := '1';
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signal dTriggerDacReset : std_logic := '1';
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-- POR value of all reset done signals are set to low.
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signal cTriggerAdcResetDone_ms : std_logic := '0';
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signal cTriggerAdcResetDone : std_logic := '0';
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signal cAdcResetDoneSticky : std_logic := '0';
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signal cTriggerDacResetDone_ms : std_logic := '0';
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signal cTriggerDacResetDone : std_logic := '0';
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signal cDacResetDoneSticky : std_logic := '0';
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attribute ASYNC_REG : string;
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attribute ASYNC_REG of dTriggerAdcReset : signal is "TRUE";
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attribute ASYNC_REG of dTriggerDacReset : signal is "TRUE";
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attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE";
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attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE";
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attribute ASYNC_REG of dTriggerAdcReset_ms : signal is "TRUE";
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attribute ASYNC_REG of dTriggerDacReset_ms : signal is "TRUE";
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attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
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attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
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begin
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-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
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rAdcEnableData <= '1';
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cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
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cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
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cSoftwareStatus <= (
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kADC_SEQ_DONE => cAdcResetDoneSticky,
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kDAC_SEQ_DONE => cDacResetDoneSticky,
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others => '0'
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);
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-----------------------------------------------------------------------------
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-- High-Level Resets Using ConfigClk
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-----------------------------------------------------------------------------
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-- Pass the master FSM reset around to the other clock domains and then
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-- return them back to the ConfigClk domain. This is also a handy way to
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-- prove all your clocks are toggling to some extent.
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-----------------------------------------------------------------------------
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SeqResetDataClk : process(DataClk)
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begin
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if rising_edge(DataClk) then
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-- double-syncs have no sync reset!
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dTriggerAdcReset_ms <= cTriggerAdcReset;
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dTriggerAdcReset <= dTriggerAdcReset_ms;
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dTriggerDacReset_ms <= cTriggerDacReset;
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dTriggerDacReset <= dTriggerDacReset_ms;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Reset Sequence Done Status
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-----------------------------------------------------------------------------
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-- Now back to ConfigClk! We provide the status for all software controlled
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-- resets. We move the signal from ConfigClk to DataClk domain and move it
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-- back to ConfigClk domain. This just proves that DataClk is toggling and
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-- the reset requested by software is sampled in the DataClk.
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-----------------------------------------------------------------------------
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SeqResetDone : process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
|
||||
-- double-syncs have no sync reset!
|
||||
cTriggerAdcResetDone_ms <= dTriggerAdcReset;
|
||||
cTriggerAdcResetDone <= cTriggerAdcResetDone_ms;
|
||||
cTriggerDacResetDone_ms <= dTriggerDacReset;
|
||||
cTriggerDacResetDone <= cTriggerDacResetDone_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- ADC reset done
|
||||
SwAdcResetDone: process(ConfigClk)
|
||||
begin
|
||||
if rising_edge(ConfigClk) then
|
||||
cTriggerAdcResetDlyd <= cTriggerAdcReset;
|
||||
-- De-assert reset status on the rising edge of SW ADC reset.
|
||||
if cTriggerAdcReset = '1' and cTriggerAdcResetDlyd = '0' then
|
||||
cAdcResetDoneSticky <= '0';
|
||||
-- Assert and hold the ADC reset status on ADC reset strobe.
|
||||
elsif cTriggerAdcResetDone = '1' then
|
||||
cAdcResetDoneSticky <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process SwAdcResetDone;
|
||||
|
||||
-- DAC reset done
|
||||
SwDacResetDone: process(ConfigClk)
|
||||
begin
|
||||
if rising_edge(ConfigClk) then
|
||||
cTriggerDacResetDlyd <= cTriggerDacReset;
|
||||
-- De-assert reset status on the rising edge of SW DAC reset.
|
||||
if cTriggerDacReset = '1' and cTriggerDacResetDlyd = '0' then
|
||||
cDacResetDoneSticky <= '0';
|
||||
-- Assert and hold the DAC reset status on DAC reset strobe.
|
||||
elsif cTriggerDacResetDone = '1' then
|
||||
cDacResetDoneSticky <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process SwDacResetDone;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- rf_reset Instances
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
AdcResets: entity work.rf_reset (RTL)
|
||||
port map (
|
||||
DataClk => DataClk,
|
||||
PllRefClk => PllRefClk,
|
||||
RfClk => RfClk,
|
||||
RfClk2x => RfClk2x,
|
||||
DataClk2x => DataClk2x,
|
||||
dTimedReset => dAdcResetPulse,
|
||||
dSwReset => dTriggerAdcReset,
|
||||
dReset_n => dAdcDataOutReset_n,
|
||||
d2Reset_n => open,
|
||||
r2Reset_n => r2AdcFirReset_n,
|
||||
rAxiReset_n => rAdcRfdcAxiReset_n,
|
||||
rReset_n => rAdcGearboxReset_n
|
||||
);
|
||||
|
||||
DacResets: entity work.rf_reset (RTL)
|
||||
port map (
|
||||
DataClk => DataClk,
|
||||
PllRefClk => PllRefClk,
|
||||
RfClk => RfClk,
|
||||
RfClk2x => RfClk2x,
|
||||
DataClk2x => DataClk2x,
|
||||
dTimedReset => dDacResetPulse,
|
||||
dSwReset => dTriggerDacReset,
|
||||
dReset_n => dDacDataInReset_n,
|
||||
d2Reset_n => d2DacFirReset_n,
|
||||
r2Reset_n => r2DacFirReset_n,
|
||||
rAxiReset_n => rDacRfdcAxiReset_n,
|
||||
rReset_n => rDacGearboxReset_n
|
||||
);
|
||||
|
||||
end RTL;
|
||||
Reference in New Issue
Block a user