mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/rf/sim/tb_rf_nco_reset.vhd

@@ -21,7 +21,9 @@ end tb_rf_nco_reset;
 architecture RTL of tb_rf_nco_reset is
 
   signal cAdc0xNcoUpdateReq      : std_logic;
+  signal cAdc1xNcoUpdateReq      : std_logic;
   signal cAdc2xNcoUpdateReq      : std_logic;
+  signal cAdc3xNcoUpdateReq      : std_logic;
   signal cDac0xNcoUpdateReq      : std_logic;
   signal cDac0xSysrefIntGating   : std_logic;
   signal cDac0xSysrefIntReenable : std_logic;
@@ -33,7 +35,9 @@ architecture RTL of tb_rf_nco_reset is
   signal cDac0xNcoUpdateBusy : std_logic_vector(1 downto 0) := "00";
   signal dStartNcoReset      : std_logic := '0';
   signal cAdc0xNcoUpdateBusy : std_logic := '0';
+  signal cAdc1xNcoUpdateBusy : std_logic := '0';
   signal cAdc2xNcoUpdateBusy : std_logic := '0';
+  signal cAdc3xNcoUpdateBusy : std_logic := '0';
   signal cDac1xNcoUpdateBusy : std_logic := '0';
 
   signal cSysref_ms, cSysref       : std_logic := '0';
@@ -100,8 +104,12 @@ begin
       cDac1xNcoUpdateReq      => cDac1xNcoUpdateReq,
       cAdc0xNcoUpdateBusy     => cAdc0xNcoUpdateBusy,
       cAdc0xNcoUpdateReq      => cAdc0xNcoUpdateReq,
+      cAdc1xNcoUpdateBusy     => cAdc1xNcoUpdateBusy,
+      cAdc1xNcoUpdateReq      => cAdc1xNcoUpdateReq,
       cAdc2xNcoUpdateBusy     => cAdc2xNcoUpdateBusy,
       cAdc2xNcoUpdateReq      => cAdc2xNcoUpdateReq,
+      cAdc3xNcoUpdateBusy     => cAdc3xNcoUpdateBusy,
+      cAdc3xNcoUpdateReq      => cAdc3xNcoUpdateReq,
       cNcoPhaseRst            => cNcoPhaseRst,
       cNcoUpdateEn            => cNcoUpdateEn,
       dNcoResetDone           => dNcoResetDone
@@ -180,7 +188,9 @@ begin
           cRfdcNcoState <= CheckUpdate;
           cDac1xNcoUpdateBusy <= cDac1xNcoUpdateReq;
           cAdc0xNcoUpdateBusy <= cAdc0xNcoUpdateReq;
+          cAdc1xNcoUpdateBusy <= cAdc1xNcoUpdateReq;
           cAdc2xNcoUpdateBusy <= cAdc2xNcoUpdateReq;
+          cAdc3xNcoUpdateBusy <= cAdc3xNcoUpdateReq;
 
         -- It takes 5 clock cycles to update each RFDC internal registers with
         -- the used request change. In rf_nco_reset entity, we only want to
@@ -194,7 +204,9 @@ begin
             cDac0xNcoUpdateBusy <= "10"; --Indicates that SYSREF is gated.
             cDac1xNcoUpdateBusy <= '0';
             cAdc0xNcoUpdateBusy <= '0';
+            cAdc1xNcoUpdateBusy <= '0';
             cAdc2xNcoUpdateBusy <= '0';
+            cAdc3xNcoUpdateBusy <= '0';
           end if;
           cWrCount <= cWrCount + 1;