mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/rf/common/capture_sysref.v

@@ -7,8 +7,15 @@
 //
 // Description:
 //
-//   Capture SYSREF and transfer it to the higher clock domain. Module incurs
-//   in 2 pll_ref_clk cycles + 1 rfdc_clk cycle of delay.
+//   Capture SYSREF and transfer it to the higher clock domain.
+//   For X410, module incurs in 2 pll_ref_clk cycles + 1 rfdc_clk
+//   cycle of delay. For X440, module synchronizes to each
+//   pll_ref_clk and rfdc_clk separately, incurring in 2 cycles
+//   for each clock.
+//
+// Parameters:
+//
+//   DEVICE_TYPE     : Type of device for which SYSREF is synchronized.
 //
 
 module capture_sysref (
@@ -25,7 +32,9 @@ module capture_sysref (
   output wire sysref_out_rclk  // RFDC output  (Domain: rfdc_clk).
 );
 
-  reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg sysref_pclk_ms = 1'b0;
+  reg sysref_pclk = 1'b0;
+  reg sysref_rclk = 1'b0;
 
   // Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
   // in case static timing isn't met so as not to destroy downstream logic.