mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/rf/400m/rf_core_400m.v

@@ -101,8 +101,9 @@ module rf_core_400m (
 
   // Control/status vectors from/to RFDC.
   // Notice these are all in the s_axi_config_clk domain.
-  output wire [15:0] dsp_info_sclk,
+  output wire [9:0] dsp_info_sclk,
   output wire [15:0] axi_status_sclk,
+  output wire [15:0] rfdc_info_sclk,
 
   // Resets.
   input wire adc_data_out_resetn_dclk,
@@ -117,8 +118,8 @@ module rf_core_400m (
   output wire [95:0] version_info
 );
 
-  `include "../../regmap/rfdc_regs_regmap_utils.vh"
-  `include "../../regmap/versioning_regs_regmap_utils.vh"
+  `include "../../regmap/x410/rfdc_regs_regmap_utils.vh"
+  `include "../../regmap/x410/versioning_regs_regmap_utils.vh"
   `include "../../regmap/versioning_utils.vh"
 
   // Fixed for this implementation
@@ -181,10 +182,14 @@ module rf_core_400m (
   );
 
   // Drive the DSP info vector with information on this specific DSP chain.
-  assign dsp_info_sclk[FABRIC_DSP_BW_MSB    :FABRIC_DSP_BW]     = FABRIC_DSP_BW_400M;
   assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS;
   assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS;
 
+  // This RF core always consumes 8 SPC from the gearbox per I/Q signal
+  assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
+  assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
+  assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd3;
+
   //---------------------------------------------------------------------------
   // ADC Post-Processing
   //---------------------------------------------------------------------------