mpm/fpga: x4xx: Major updates in preparation for future devices

FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223

top/x400/rf/200m/rf_core_200m.v

@@ -89,8 +89,9 @@ module rf_core_200m (
 
   // Control/status vectors from/to RFDC.
   // Notice these are all in the s_axi_config_clk domain.
-  output reg  [15:0] dsp_info_sclk,
+  output wire  [9:0] dsp_info_sclk,
   output wire [15:0] axi_status_sclk,
+  output wire [15:0] rfdc_info_sclk,
 
   // Resets.
   input wire adc_data_out_resetn_dclk,
@@ -105,7 +106,7 @@ module rf_core_200m (
   output wire [95:0] version_info
 );
 
-  `include "../../regmap/rfdc_regs_regmap_utils.vh"
+  `include "../../regmap/x410/rfdc_regs_regmap_utils.vh"
 
   //---------------------------------------------------------------------------
   // 400 MHz RF Core
@@ -170,11 +171,12 @@ module rf_core_200m (
     .version_info              (version_info)
   );
 
-  // Change reported bandwidth 200 MHz
-  always @(*) begin
-    dsp_info_sclk                                    <= dsp_info_sclk_400m;
-    dsp_info_sclk[FABRIC_DSP_BW_MSB : FABRIC_DSP_BW] <= FABRIC_DSP_BW_200M;
-  end
+  assign dsp_info_sclk = dsp_info_sclk_400m;
+
+  // This RF core always consumes 8 SPC from the gearbox per I/Q signal
+  assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
+  assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
+  assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd6;
 
 
   //---------------------------------------------------------------------------