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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd
-663
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@@ -1,663 +0,0 @@
---------------------------------------------------------------------
--
-- Copyright 2022 Ettus Research, A National Instruments Brand
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: PkgRFDC_REGS_REGMAP.vhd
--
-- Purpose:
-- The constants in this file are autogenerated by XmlParse.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgRFDC_REGS_REGMAP is
--===============================================================================
-- A numerically ordered list of registers and their HDL source files
--===============================================================================
-- MMCM : 0x0 (common_regs.v)
-- INVERT_IQ_REG : 0x10000 (common_regs.v)
-- MMCM_RESET_REG : 0x11000 (common_regs.v)
-- RF_RESET_CONTROL_REG : 0x12000 (common_regs.v)
-- RF_RESET_STATUS_REG : 0x12008 (common_regs.v)
-- RF_AXI_STATUS_REG : 0x13000 (common_regs.v)
-- FABRIC_DSP_REG : 0x13008 (common_regs.v)
-- CALIBRATION_DATA : 0x14000 (common_regs.v)
-- CALIBRATION_ENABLE : 0x14008 (common_regs.v)
-- THRESHOLD_STATUS : 0x15000 (common_regs.v)
-- RF_PLL_CONTROL_REG : 0x16000 (common_regs.v)
-- RF_PLL_STATUS_REG : 0x16008 (common_regs.v)
--===============================================================================
-- RegTypes
--===============================================================================
--===============================================================================
-- Register Group RFDC_REGS
--===============================================================================
-- Enumerated type FABRIC_DSP_BW_ENUM
constant kFABRIC_DSP_BW_ENUMSize : integer := 4;
constant kFABRIC_DSP_BW_NONE : integer := 0; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
constant kFABRIC_DSP_BW_100M : integer := 100; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
constant kFABRIC_DSP_BW_200M : integer := 200; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
constant kFABRIC_DSP_BW_400M : integer := 400; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
-- MMCM Window (from common_regs.v)
constant kMMCM : integer := 16#0#; -- Window Offset
constant kMMCMSize: integer := 16#10000#; -- size in bytes
--function kMMCMRec return XReg2_t; -- Window Record function commented out due to programmable attributes
-- INVERT_IQ_REG Register (from common_regs.v)
constant kINVERT_IQ_REG : integer := 16#10000#; -- Register Offset
constant kINVERT_IQ_REGSize: integer := 32; -- register width in bits
constant kINVERT_IQ_REGMask : std_logic_vector(31 downto 0) := X"0000ffff";
constant kINVERT_DB0_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC0_IQMsb : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC0_IQ : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC1_IQMsb : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC1_IQ : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC2_IQMsb : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC2_IQ : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB0_ADC3_IQMsb : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB0_ADC3_IQ : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB1_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC0_IQMsb : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC0_IQ : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC1_IQMsb : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC1_IQ : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC2_IQMsb : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC2_IQ : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB1_ADC3_IQMsb : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB1_ADC3_IQ : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB0_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC0_IQMsb : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC0_IQ : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC1_IQMsb : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC1_IQ : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC2_IQMsb : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC2_IQ : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB0_DAC3_IQMsb : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB0_DAC3_IQ : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB1_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC0_IQMsb : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC0_IQ : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC1_IQMsb : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC1_IQ : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC2_IQMsb : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC2_IQ : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
constant kINVERT_DB1_DAC3_IQMsb : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
constant kINVERT_DB1_DAC3_IQ : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
--function kINVERT_IQ_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- MMCM_RESET_REG Register (from common_regs.v)
constant kMMCM_RESET_REG : integer := 16#11000#; -- Register Offset
constant kMMCM_RESET_REGSize: integer := 32; -- register width in bits
constant kMMCM_RESET_REGMask : std_logic_vector(31 downto 0) := X"00000001";
constant kRESET_MMCMSize : integer := 1; --MMCM_RESET_REG:RESET_MMCM
constant kRESET_MMCMMsb : integer := 0; --MMCM_RESET_REG:RESET_MMCM
constant kRESET_MMCM : integer := 0; --MMCM_RESET_REG:RESET_MMCM
--function kMMCM_RESET_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_RESET_CONTROL_REG Register (from common_regs.v)
constant kRF_RESET_CONTROL_REG : integer := 16#12000#; -- Register Offset
constant kRF_RESET_CONTROL_REGSize: integer := 32; -- register width in bits
constant kRF_RESET_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00000331";
constant kFSM_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:FSM_RESET
constant kFSM_RESETMsb : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET
constant kFSM_RESET : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET
constant kADC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_RESETMsb : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_RESET : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kADC_ENABLEMsb : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kADC_ENABLE : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kDAC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_RESETMsb : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_RESET : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:DAC_ENABLE
constant kDAC_ENABLEMsb : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE
constant kDAC_ENABLE : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE
--function kRF_RESET_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_RESET_STATUS_REG Register (from common_regs.v)
constant kRF_RESET_STATUS_REG : integer := 16#12008#; -- Register Offset
constant kRF_RESET_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_RESET_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00000888";
constant kFSM_RESET_DONESize : integer := 1; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kFSM_RESET_DONEMsb : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kFSM_RESET_DONE : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kADC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kADC_SEQ_DONEMsb : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kADC_SEQ_DONE : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kDAC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
constant kDAC_SEQ_DONEMsb : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
constant kDAC_SEQ_DONE : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
--function kRF_RESET_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_AXI_STATUS_REG Register (from common_regs.v)
constant kRF_AXI_STATUS_REG : integer := 16#13000#; -- Register Offset
constant kRF_AXI_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_AXI_STATUS_REGMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kRFDC_DAC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TREADYMsb : integer := 1; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TREADY : integer := 0; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_DAC_TVALIDMsb : integer := 3; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_DAC_TVALID : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_ADC_Q_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_Q_TREADYMsb : integer := 5; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_Q_TREADY : integer := 4; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_I_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_I_TREADYMsb : integer := 7; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_I_TREADY : integer := 6; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_Q_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_Q_TVALIDMsb : integer := 9; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_Q_TVALID : integer := 8; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_I_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kRFDC_ADC_I_TVALIDMsb : integer := 11; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kRFDC_ADC_I_TVALID : integer := 10; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kUSER_ADC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TVALIDMsb : integer := 13; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TVALID : integer := 12; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kUSER_ADC_TREADYMsb : integer := 15; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kUSER_ADC_TREADY : integer := 14; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kRFDC_DAC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TREADY_DB1Msb : integer := 17; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TREADY_DB1 : integer := 16; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_DAC_TVALID_DB1Msb : integer := 19; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_DAC_TVALID_DB1 : integer := 18; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_ADC_Q_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_Q_TREADY_DB1Msb : integer := 21; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_Q_TREADY_DB1 : integer := 20; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1Msb : integer := 23; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1 : integer := 22; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_Q_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_Q_TVALID_DB1Msb : integer := 25; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_Q_TVALID_DB1 : integer := 24; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1Msb : integer := 27; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1 : integer := 26; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kUSER_ADC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TVALID_DB1Msb : integer := 29; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TVALID_DB1 : integer := 28; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
constant kUSER_ADC_TREADY_DB1Msb : integer := 31; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
constant kUSER_ADC_TREADY_DB1 : integer := 30; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
--function kRF_AXI_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- FABRIC_DSP_REG Register (from common_regs.v)
constant kFABRIC_DSP_REG : integer := 16#13008#; -- Register Offset
constant kFABRIC_DSP_REGSize: integer := 32; -- register width in bits
constant kFABRIC_DSP_REGMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kFABRIC_DSP_BWSize : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_BWMsb : integer := 11; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_BW : integer := 0; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_RX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_RX_CNTMsb : integer := 13; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_RX_CNT : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_TX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_TX_CNTMsb : integer := 15; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_TX_CNT : integer := 14; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_BW_DB1Size : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_BW_DB1Msb : integer := 27; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_BW_DB1 : integer := 16; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_RX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_RX_CNT_DB1Msb : integer := 29; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_RX_CNT_DB1 : integer := 28; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1Msb : integer := 31; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1 : integer := 30; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
--function kFABRIC_DSP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- CALIBRATION_DATA Register (from common_regs.v)
constant kCALIBRATION_DATA : integer := 16#14000#; -- Register Offset
constant kCALIBRATION_DATASize: integer := 32; -- register width in bits
constant kCALIBRATION_DATAMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kI_DATASize : integer := 16; --CALIBRATION_DATA:I_DATA
constant kI_DATAMsb : integer := 15; --CALIBRATION_DATA:I_DATA
constant kI_DATA : integer := 0; --CALIBRATION_DATA:I_DATA
constant kQ_DATASize : integer := 16; --CALIBRATION_DATA:Q_DATA
constant kQ_DATAMsb : integer := 31; --CALIBRATION_DATA:Q_DATA
constant kQ_DATA : integer := 16; --CALIBRATION_DATA:Q_DATA
--function kCALIBRATION_DATARec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- CALIBRATION_ENABLE Register (from common_regs.v)
constant kCALIBRATION_ENABLE : integer := 16#14008#; -- Register Offset
constant kCALIBRATION_ENABLESize: integer := 32; -- register width in bits
constant kCALIBRATION_ENABLEMask : std_logic_vector(31 downto 0) := X"00000033";
constant kENABLE_CALIBRATION_DATA_0Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_0Msb : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_0 : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_1Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_1Msb : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_1 : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_2Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_2Msb : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_2 : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_3Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
constant kENABLE_CALIBRATION_DATA_3Msb : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
constant kENABLE_CALIBRATION_DATA_3 : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
--function kCALIBRATION_ENABLERec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- THRESHOLD_STATUS Register (from common_regs.v)
constant kTHRESHOLD_STATUS : integer := 16#15000#; -- Register Offset
constant kTHRESHOLD_STATUSSize: integer := 32; -- register width in bits
constant kTHRESHOLD_STATUSMask : std_logic_vector(31 downto 0) := X"00000f0f";
constant kADC0_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD1Msb : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD1 : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_01_THRESHOLD2Msb : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_01_THRESHOLD2 : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD1Msb : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD1 : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC0_23_THRESHOLD2Msb : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC0_23_THRESHOLD2 : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC2_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD1Msb : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD1 : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_01_THRESHOLD2Msb : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_01_THRESHOLD2 : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD1Msb : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD1 : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
constant kADC2_23_THRESHOLD2Msb : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
constant kADC2_23_THRESHOLD2 : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
--function kTHRESHOLD_STATUSRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_PLL_CONTROL_REG Register (from common_regs.v)
constant kRF_PLL_CONTROL_REG : integer := 16#16000#; -- Register Offset
constant kRF_PLL_CONTROL_REGSize: integer := 32; -- register width in bits
constant kRF_PLL_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00011111";
constant kENABLE_DATA_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLKMsb : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLK : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_DATA_CLK_2XMsb : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_DATA_CLK_2X : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_RF_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLKMsb : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLK : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kENABLE_RF_CLK_2XMsb : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kENABLE_RF_CLK_2X : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kCLEAR_DATA_CLK_UNLOCKEDSize : integer := 1; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
constant kCLEAR_DATA_CLK_UNLOCKEDMsb : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
constant kCLEAR_DATA_CLK_UNLOCKED : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
--function kRF_PLL_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_PLL_STATUS_REG Register (from common_regs.v)
constant kRF_PLL_STATUS_REG : integer := 16#16008#; -- Register Offset
constant kRF_PLL_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_PLL_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00110000";
constant kDATA_CLK_PLL_UNLOCKED_STICKYSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_UNLOCKED_STICKYMsb : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_UNLOCKED_STICKY : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_LOCKEDSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
constant kDATA_CLK_PLL_LOCKEDMsb : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
constant kDATA_CLK_PLL_LOCKED : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
--function kRF_PLL_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
end package;
package body PkgRFDC_REGS_REGMAP is
-- function kMMCMRec not implemented because MMCM has programmable attributes
---- Return the record of window kMMCM
--function kMMCMRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"0");
-- Rec.size := kMMCMSize;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00");
-- Rec.rmask := XRegResize(X"00");
-- Rec.strobemask := XRegResize(X"00");
-- Rec.clearablemask := XRegResize(X"00");
-- Rec.iswin := true;
-- --synopsys translate_off
-- Rec.name := rs("MMCM");
-- --synopsys translate_on
-- return Rec;
--end function kMMCMRec;
-- function kINVERT_IQ_REGRec not implemented because INVERT_IQ_REG has programmable attributes
---- Return the record of register kINVERT_IQ_REG
--function kINVERT_IQ_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"10000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"0000ffff");
-- Rec.rmask := XRegResize(X"0000ffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("INVERT_IQ_REG");
-- --synopsys translate_on
-- return Rec;
--end function kINVERT_IQ_REGRec;
-- function kMMCM_RESET_REGRec not implemented because MMCM_RESET_REG has programmable attributes
---- Return the record of register kMMCM_RESET_REG
--function kMMCM_RESET_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"11000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000001");
-- Rec.rmask := XRegResize(X"00000001");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("MMCM_RESET_REG");
-- --synopsys translate_on
-- return Rec;
--end function kMMCM_RESET_REGRec;
-- function kRF_RESET_CONTROL_REGRec not implemented because RF_RESET_CONTROL_REG has programmable attributes
---- Return the record of register kRF_RESET_CONTROL_REG
--function kRF_RESET_CONTROL_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"12000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000331");
-- Rec.rmask := XRegResize(X"00000331");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_RESET_CONTROL_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_RESET_CONTROL_REGRec;
-- function kRF_RESET_STATUS_REGRec not implemented because RF_RESET_STATUS_REG has programmable attributes
---- Return the record of register kRF_RESET_STATUS_REG
--function kRF_RESET_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"12008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"00000888");
-- Rec.rmask := XRegResize(X"00000888");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_RESET_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_RESET_STATUS_REGRec;
-- function kRF_AXI_STATUS_REGRec not implemented because RF_AXI_STATUS_REG has programmable attributes
---- Return the record of register kRF_AXI_STATUS_REG
--function kRF_AXI_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"13000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb;
-- Rec.msblookupw(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb;
-- Rec.msblookupw(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb;
-- Rec.msblookupw(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb;
-- Rec.msblookupw(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb;
-- Rec.msblookupw(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb;
-- Rec.msblookupw(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb;
-- Rec.msblookupw(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb;
-- Rec.msblookupw(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb;
-- Rec.msblookupw(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb;
-- Rec.msblookupw(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb;
-- Rec.msblookupr(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb;
-- Rec.msblookupr(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb;
-- Rec.msblookupr(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb;
-- Rec.msblookupr(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb;
-- Rec.msblookupr(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb;
-- Rec.msblookupr(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb;
-- Rec.msblookupr(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb;
-- Rec.msblookupr(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb;
-- Rec.msblookupr(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb;
-- Rec.msblookupr(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_AXI_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_AXI_STATUS_REGRec;
-- function kFABRIC_DSP_REGRec not implemented because FABRIC_DSP_REG has programmable attributes
---- Return the record of register kFABRIC_DSP_REG
--function kFABRIC_DSP_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"13008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- Rec.initialvalue := XRegResize(X"00000000");
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb;
-- Rec.msblookupw(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb;
-- Rec.msblookupw(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb;
-- Rec.msblookupw(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb;
-- Rec.msblookupw(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb;
-- Rec.msblookupw(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb;
-- Rec.msblookupr(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb;
-- Rec.msblookupr(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb;
-- Rec.msblookupr(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("FABRIC_DSP_REG");
-- --synopsys translate_on
-- return Rec;
--end function kFABRIC_DSP_REGRec;
-- function kCALIBRATION_DATARec not implemented because CALIBRATION_DATA has programmable attributes
---- Return the record of register kCALIBRATION_DATA
--function kCALIBRATION_DATARec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"14000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kI_DATA) := kI_DATAMsb;
-- Rec.msblookupw(kQ_DATA) := kQ_DATAMsb;
-- Rec.msblookupr(kI_DATA) := kI_DATAMsb;
-- Rec.msblookupr(kQ_DATA) := kQ_DATAMsb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("CALIBRATION_DATA");
-- --synopsys translate_on
-- return Rec;
--end function kCALIBRATION_DATARec;
-- function kCALIBRATION_ENABLERec not implemented because CALIBRATION_ENABLE has programmable attributes
---- Return the record of register kCALIBRATION_ENABLE
--function kCALIBRATION_ENABLERec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"14008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000033");
-- Rec.rmask := XRegResize(X"00000033");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("CALIBRATION_ENABLE");
-- --synopsys translate_on
-- return Rec;
--end function kCALIBRATION_ENABLERec;
-- function kTHRESHOLD_STATUSRec not implemented because THRESHOLD_STATUS has programmable attributes
---- Return the record of register kTHRESHOLD_STATUS
--function kTHRESHOLD_STATUSRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"15000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000f0f");
-- Rec.rmask := XRegResize(X"00000f0f");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("THRESHOLD_STATUS");
-- --synopsys translate_on
-- return Rec;
--end function kTHRESHOLD_STATUSRec;
-- function kRF_PLL_CONTROL_REGRec not implemented because RF_PLL_CONTROL_REG has programmable attributes
---- Return the record of register kRF_PLL_CONTROL_REG
--function kRF_PLL_CONTROL_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"16000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00011111");
-- Rec.rmask := XRegResize(X"00011111");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_PLL_CONTROL_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_PLL_CONTROL_REGRec;
-- function kRF_PLL_STATUS_REGRec not implemented because RF_PLL_STATUS_REG has programmable attributes
---- Return the record of register kRF_PLL_STATUS_REG
--function kRF_PLL_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"16008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"00110000");
-- Rec.rmask := XRegResize(X"00110000");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_PLL_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_PLL_STATUS_REGRec;
end package body;
top/x400/regmap/core_regs_regmap_utils.vh
+10 -5
View File
@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,7 +13,8 @@
// GLOBAL_REGS : 0x0 (x4xx_core_common.v)
// VERSIONING_REGS : 0xC00 (x4xx_core_common.v)
// TIMEKEEPER : 0x1000 (x4xx_core_common.v)
// TIMEKEEPER_A : 0x1000 (x4xx_core_common.v)
// TIMEKEEPER_B : 0x1100 (x4xx_core_common.v)
// DIO : 0x2000 (x4xx_core_common.v)
//===============================================================================
@@ -32,9 +33,13 @@
localparam VERSIONING_REGS = 'hC00; // Window Offset
localparam VERSIONING_REGS_SIZE = 'h400; // size in byte
// TIMEKEEPER Window (from x4xx_core_common.v)
localparam TIMEKEEPER = 'h1000; // Window Offset
localparam TIMEKEEPER_SIZE = 'h20; // size in bytes
// TIMEKEEPER_A Window (from x4xx_core_common.v)
localparam TIMEKEEPER_A = 'h1000; // Window Offset
localparam TIMEKEEPER_A_SIZE = 'h20; // size in bytes
// TIMEKEEPER_B Window (from x4xx_core_common.v)
localparam TIMEKEEPER_B = 'h1100; // Window Offset
localparam TIMEKEEPER_B_SIZE = 'h20; // size in bytes
// DIO Window (from x4xx_core_common.v)
localparam DIO = 'h2000; // Window Offset
top/x400/regmap/cpld_interface_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/dig_ifc_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/dio_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/global_regs_regmap_utils.vh
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// PPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam PPS_CTRL_REG = 'h1C; // Register Offset
localparam PPS_CTRL_REG_SIZE = 32; // register width in bits
localparam PPS_CTRL_REG_MASK = 32'hB3FFFFFF;
localparam PPS_CTRL_REG_MASK = 32'hBFFFFFFF;
localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PRC_RC_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC1_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 27; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 26; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC0_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
@@ -174,8 +177,6 @@
localparam CHDR_CLK_SIZE = 32; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK_MSB = 31; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK = 0; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK_ENUM_SIZE = 1;
localparam CHDR_CLK_VALUE = 'hBEBC200; // enum value
// CHDR_CLK_COUNT_REG Register (from x4xx_global_regs.v)
localparam CHDR_CLK_COUNT_REG = 'h24; // Register Offset
top/x400/regmap/gpio_atr_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/pl_cpld_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/radio_ctrlport_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/radio_dio_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/rfdc_timing_regmap_utils.vh
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//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/x410/PkgRFDC_REGS_REGMAP.vhd
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top/x400/regmap/x410/rfdc_regs_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// MMCM : 0x0 (x410_rfdc_regs.v)
// INVERT_DB0_IQ_REG : 0x10000 (x410_rfdc_regs.v)
// INVERT_DB1_IQ_REG : 0x10800 (x410_rfdc_regs.v)
// MMCM_RESET_REG : 0x11000 (x410_rfdc_regs.v)
// RF_RESET_CONTROL_REG : 0x12000 (x410_rfdc_regs.v)
// RF_RESET_STATUS_REG : 0x12008 (x410_rfdc_regs.v)
// RF_AXI_STATUS_REG : 0x13000 (x410_rfdc_regs.v)
// FABRIC_DSP_REG : 0x13008 (x410_rfdc_regs.v)
// CALIBRATION_DATA : 0x14000 (x410_rfdc_regs.v)
// CALIBRATION_ENABLE : 0x14008 (x410_rfdc_regs.v)
// THRESHOLD_STATUS : 0x15000 (x410_rfdc_regs.v)
// RF_PLL_CONTROL_REG : 0x16000 (x410_rfdc_regs.v)
// RF_PLL_STATUS_REG : 0x16008 (x410_rfdc_regs.v)
// ADC_TILEMAP_REG : 0x17000 (x410_rfdc_regs.v)
// DAC_TILEMAP_REG : 0x17008 (x410_rfdc_regs.v)
// RFDC_INFO_REG : 0x18000 (x410_rfdc_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// ADC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam ADC_TILEMAP_REGTYPE_SIZE = 32;
localparam ADC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam ADC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE = 0; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE = 4; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK = 6; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE = 8; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK = 10; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE = 12; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK = 14; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE = 16; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK = 18; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE = 20; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK = 22; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE = 24; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK = 26; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE = 28; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK = 30; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
// DAC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam DAC_TILEMAP_REGTYPE_SIZE = 32;
localparam DAC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam DAC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE = 0; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE = 4; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK = 6; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE = 8; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK = 10; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE = 12; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK = 14; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE = 16; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK = 18; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE = 20; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK = 22; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE = 24; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK = 26; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE = 28; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK = 30; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
// FABRIC_DSP_REGTYPE Type (from common_regs.v)
localparam FABRIC_DSP_REGTYPE_SIZE = 32;
localparam FABRIC_DSP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam FABRIC_DSP_RX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT_MSB = 3; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT = 0; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_TX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT_MSB = 7; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_RESERVED_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED_MSB = 9; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED = 8; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1_MSB = 13; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1 = 10; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_MSB = 17; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1 = 14; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_RESERVED_DB1_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1_MSB = 19; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1 = 18; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW_MSB = 31; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW = 20; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
// RF_AXI_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_AXI_STATUS_REGTYPE_SIZE = 32;
localparam RF_AXI_STATUS_REGTYPE_MASK = 32'hFFFFFFFF;
localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
// RF_RESET_CONTROL_REGTYPE Type (from common_regs.v)
localparam RF_RESET_CONTROL_REGTYPE_SIZE = 32;
localparam RF_RESET_CONTROL_REGTYPE_MASK = 32'h331;
localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
// RF_RESET_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_RESET_STATUS_REGTYPE_SIZE = 32;
localparam RF_RESET_STATUS_REGTYPE_MASK = 32'h888;
localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
// RFDC_INFO_REGTYPE Type (from common_regs.v)
localparam RFDC_INFO_REGTYPE_SIZE = 32;
localparam RFDC_INFO_REGTYPE_MASK = 32'h3FF03FF;
localparam RFDC_INFO_XTRA_RESAMP_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP_MSB = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP = 0; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_SPC_RX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX_MSB = 6; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_TX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX_MSB = 9; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX = 7; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_XTRA_RESAMP_DB1_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1_MSB = 19; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1 = 16; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_SPC_RX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1_MSB = 22; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1 = 20; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_TX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1_MSB = 25; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1 = 23; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
//===============================================================================
// Register Group RFDC_REGS
//===============================================================================
// Enumerated type FABRIC_DSP_BW_ENUM
localparam FABRIC_DSP_BW_ENUM_SIZE = 5;
localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
localparam FABRIC_DSP_BW_FULL = 'h3E8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL
// MMCM Window (from x410_rfdc_regs.v)
localparam MMCM = 'h0; // Window Offset
localparam MMCM_SIZE = 'h10000; // size in bytes
// INVERT_DB0_IQ_REG Register (from x410_rfdc_regs.v)
localparam INVERT_DB0_IQ_REG = 'h10000; // Register Offset
localparam INVERT_DB0_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB0_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
// INVERT_DB1_IQ_REG Register (from x410_rfdc_regs.v)
localparam INVERT_DB1_IQ_REG = 'h10800; // Register Offset
localparam INVERT_DB1_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB1_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ_MSB = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ_MSB = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ_MSB = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ_MSB = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ_MSB = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ_MSB = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ_MSB = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ_MSB = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
// MMCM_RESET_REG Register (from x410_rfdc_regs.v)
localparam MMCM_RESET_REG = 'h11000; // Register Offset
localparam MMCM_RESET_REG_SIZE = 32; // register width in bits
localparam MMCM_RESET_REG_MASK = 32'h1;
localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM
// RF_RESET_CONTROL_REG Register (from x410_rfdc_regs.v)
localparam RF_RESET_CONTROL_REG = 'h12000; // Register Offset
localparam RF_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF_RESET_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_RESET_STATUS_REG = 'h12008; // Register Offset
localparam RF_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF_AXI_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset
localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits
// FABRIC_DSP_REG Register (from x410_rfdc_regs.v)
localparam FABRIC_DSP_REG = 'h13008; // Register Offset
localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits
// CALIBRATION_DATA Register (from x410_rfdc_regs.v)
localparam CALIBRATION_DATA = 'h14000; // Register Offset
localparam CALIBRATION_DATA_SIZE = 32; // register width in bits
localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF;
localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA
localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA
localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA
localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA
// CALIBRATION_ENABLE Register (from x410_rfdc_regs.v)
localparam CALIBRATION_ENABLE = 'h14008; // Register Offset
localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits
localparam CALIBRATION_ENABLE_MASK = 32'h33;
localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
// THRESHOLD_STATUS Register (from x410_rfdc_regs.v)
localparam THRESHOLD_STATUS = 'h15000; // Register Offset
localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits
localparam THRESHOLD_STATUS_MASK = 32'hF0F;
localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
// RF_PLL_CONTROL_REG Register (from x410_rfdc_regs.v)
localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset
localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_PLL_CONTROL_REG_MASK = 32'h11111;
localparam ENABLE_DATA_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_MSB = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X_MSB = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_RF_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
// RF_PLL_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset
localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_PLL_STATUS_REG_MASK = 32'h110000;
localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
// ADC_TILEMAP_REG Register (from x410_rfdc_regs.v)
localparam ADC_TILEMAP_REG = 'h17000; // Register Offset
localparam ADC_TILEMAP_REG_SIZE = 32; // register width in bits
// DAC_TILEMAP_REG Register (from x410_rfdc_regs.v)
localparam DAC_TILEMAP_REG = 'h17008; // Register Offset
localparam DAC_TILEMAP_REG_SIZE = 32; // register width in bits
// RFDC_INFO_REG Register (from x410_rfdc_regs.v)
localparam RFDC_INFO_REG = 'h18000; // Register Offset
localparam RFDC_INFO_REG_SIZE = 32; // register width in bits
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: versioning_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// CURRENT_VERSION : 0x0 (x4xx_versioning_regs.v)
// OLDEST_COMPATIBLE_VERSION : 0x4 (x4xx_versioning_regs.v)
// VERSION_LAST_MODIFIED : 0x8 (x4xx_versioning_regs.v)
// RESERVED : 0xC (x4xx_versioning_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// RESERVED_TYPE Type (from x4xx_versioning_regs.v)
localparam RESERVED_TYPE_SIZE = 32;
localparam RESERVED_TYPE_MASK = 32'h0;
// TIMESTAMP_TYPE Type (from x4xx_versioning_regs.v)
localparam TIMESTAMP_TYPE_SIZE = 32;
localparam TIMESTAMP_TYPE_MASK = 32'hFFFFFFFF;
localparam HH_SIZE = 8; //TIMESTAMP_TYPE:HH
localparam HH_MSB = 7; //TIMESTAMP_TYPE:HH
localparam HH = 0; //TIMESTAMP_TYPE:HH
localparam DD_SIZE = 8; //TIMESTAMP_TYPE:DD
localparam DD_MSB = 15; //TIMESTAMP_TYPE:DD
localparam DD = 8; //TIMESTAMP_TYPE:DD
localparam MM_SIZE = 8; //TIMESTAMP_TYPE:MM
localparam MM_MSB = 23; //TIMESTAMP_TYPE:MM
localparam MM = 16; //TIMESTAMP_TYPE:MM
localparam YY_SIZE = 8; //TIMESTAMP_TYPE:YY
localparam YY_MSB = 31; //TIMESTAMP_TYPE:YY
localparam YY = 24; //TIMESTAMP_TYPE:YY
// VERSION_TYPE Type (from x4xx_versioning_regs.v)
localparam VERSION_TYPE_SIZE = 32;
localparam VERSION_TYPE_MASK = 32'hFFFFFFFF;
localparam BUILD_SIZE = 12; //VERSION_TYPE:BUILD
localparam BUILD_MSB = 11; //VERSION_TYPE:BUILD
localparam BUILD = 0; //VERSION_TYPE:BUILD
localparam MINOR_SIZE = 11; //VERSION_TYPE:MINOR
localparam MINOR_MSB = 22; //VERSION_TYPE:MINOR
localparam MINOR = 12; //VERSION_TYPE:MINOR
localparam MAJOR_SIZE = 9; //VERSION_TYPE:MAJOR
localparam MAJOR_MSB = 31; //VERSION_TYPE:MAJOR
localparam MAJOR = 23; //VERSION_TYPE:MAJOR
//===============================================================================
// Register Group VERSIONING_CONSTANTS
//===============================================================================
// Enumerated type CPLD_IFC_VERSION
localparam CPLD_IFC_VERSION_SIZE = 7;
localparam CPLD_IFC_CURRENT_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MINOR
localparam CPLD_IFC_CURRENT_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_BUILD
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam CPLD_IFC_CURRENT_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MAJOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam CPLD_IFC_VERSION_LAST_MODIFIED_TIME = 'h21011809; // CPLD_IFC_VERSION:CPLD_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type DB_GPIO_IFC_VERSION
localparam DB_GPIO_IFC_VERSION_SIZE = 7;
localparam DB_GPIO_IFC_CURRENT_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MINOR
localparam DB_GPIO_IFC_CURRENT_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_BUILD
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h20110616; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
localparam RF_CORE_100M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MINOR
localparam RF_CORE_100M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_BUILD
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_100M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MAJOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_100M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_100M_VERSION:RF_CORE_100M_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_400M_VERSION
localparam RF_CORE_400M_VERSION_SIZE = 7;
localparam RF_CORE_400M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MINOR
localparam RF_CORE_400M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_BUILD
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_400M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MAJOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_400M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_400M_VERSION:RF_CORE_400M_VERSION_LAST_MODIFIED_TIME
//===============================================================================
// Register Group VERSIONING_REGS
//===============================================================================
// Enumerated type COMPONENTS_INDEXES
localparam COMPONENTS_INDEXES_SIZE = 6;
localparam FPGA_VERSION_INDEX = 'h0; // COMPONENTS_INDEXES:FPGA_VERSION_INDEX
localparam CPLD_IFC_INDEX = 'h1; // COMPONENTS_INDEXES:CPLD_IFC_INDEX
localparam DB0_RF_CORE_INDEX = 'h2; // COMPONENTS_INDEXES:DB0_RF_CORE_INDEX
localparam DB1_RF_CORE_INDEX = 'h3; // COMPONENTS_INDEXES:DB1_RF_CORE_INDEX
localparam DB0_GPIO_IFC_INDEX = 'h4; // COMPONENTS_INDEXES:DB0_GPIO_IFC_INDEX
localparam DB1_GPIO_IFC_INDEX = 'h5; // COMPONENTS_INDEXES:DB1_GPIO_IFC_INDEX
// CURRENT_VERSION Register (from x4xx_versioning_regs.v)
localparam CURRENT_VERSION_COUNT = 64; // Number of elements in array
// OLDEST_COMPATIBLE_VERSION Register (from x4xx_versioning_regs.v)
localparam OLDEST_COMPATIBLE_VERSION_COUNT = 64; // Number of elements in array
// VERSION_LAST_MODIFIED Register (from x4xx_versioning_regs.v)
localparam VERSION_LAST_MODIFIED_COUNT = 64; // Number of elements in array
// RESERVED Register (from x4xx_versioning_regs.v)
localparam RESERVED_COUNT = 64; // Number of elements in array
// Return the offset of an element of register array CURRENT_VERSION
function integer CURRENT_VERSION (input integer i);
CURRENT_VERSION = (i * 'h10) + 'h0;
endfunction
// Return the offset of an element of register array OLDEST_COMPATIBLE_VERSION
function integer OLDEST_COMPATIBLE_VERSION (input integer i);
OLDEST_COMPATIBLE_VERSION = (i * 'h10) + 'h4;
endfunction
// Return the offset of an element of register array VERSION_LAST_MODIFIED
function integer VERSION_LAST_MODIFIED (input integer i);
VERSION_LAST_MODIFIED = (i * 'h10) + 'h8;
endfunction
// Return the offset of an element of register array RESERVED
function integer RESERVED (input integer i);
RESERVED = (i * 'h10) + 'hC;
endfunction