mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
committed by
Martin Braun
Martin Braun
co-authored by
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
Wade Fife
Ryan Marlow
Martin Braun
Humberto Jimenez
parent
ffdcc016cc
commit
adf6f576c6
@@ -0,0 +1,32 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_AXI_INTER_2X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x512_512_bd/, \
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axi_inter_2x512_512_bd.tcl \
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)
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IP_AXI_INTER_2X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
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axi_inter_2x512_512_bd.tcl \
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)
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IP_AXI_INTER_2X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
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axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.bd \
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)
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BD_AXI_INTER_2X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
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axi_inter_2x512_512_bd.bd.out \
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axi_inter_2x512_512_bd/axi_inter_2x512_512_bd_ooc.xdc \
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axi_inter_2x512_512_bd/synth/axi_inter_2x512_512_bd.v \
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)
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.INTERMEDIATE: IP_AXI_INTER_2X512_512_BD_TRGT
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$(IP_AXI_INTER_2X512_512_BD_SRCS) $(BD_AXI_INTER_2X512_512_BD_OUTS) $(IP_AXI_INTER_2X512_512_BDTCL_SRCS): IP_AXI_INTER_2X512_512_BD_TRGT
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@:
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IP_AXI_INTER_2X512_512_BD_TRGT: $(IP_AXI_INTER_2X512_512_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,axi_inter_2x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
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@@ -0,0 +1,380 @@
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################################################################
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# This is a generated script based on design: axi_inter_2x512_512_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source axi_inter_2x512_512_bd_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name axi_inter_2x512_512_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_clock_converter:2.1\
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xilinx.com:ip:axi_crossbar:2.1\
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xilinx.com:ip:axi_data_fifo:2.1\
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xilinx.com:ip:axi_register_slice:2.1\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.PROTOCOL {AXI4} \
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] $M0_AXI
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set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {1} \
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CONFIG.HAS_CACHE {1} \
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CONFIG.HAS_LOCK {1} \
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CONFIG.HAS_PROT {1} \
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CONFIG.HAS_QOS {1} \
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CONFIG.HAS_REGION {1} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {1} \
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CONFIG.ID_WIDTH {1} \
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CONFIG.MAX_BURST_LENGTH {256} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {1} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $S0_AXI
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set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.FREQ_HZ {350000000} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {1} \
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CONFIG.HAS_CACHE {1} \
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CONFIG.HAS_LOCK {1} \
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CONFIG.HAS_PROT {1} \
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CONFIG.HAS_QOS {1} \
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CONFIG.HAS_REGION {1} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {1} \
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CONFIG.ID_WIDTH {1} \
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CONFIG.MAX_BURST_LENGTH {256} \
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CONFIG.NUM_READ_OUTSTANDING {2} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {2} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {1} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $S1_AXI
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# Create ports
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set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
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CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
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] $M0_AXI_ACLK
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set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_LOW} \
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] $M0_AXI_ARESETN
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set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
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CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \
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] $S0_AXI_ACLK
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set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
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# Create instance: axi_clock_converter_0, and set properties
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set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
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# Create instance: axi_crossbar_0, and set properties
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set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
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set_property -dict [ list \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.ID_WIDTH {2} \
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CONFIG.NUM_MI {1} \
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CONFIG.NUM_SI {2} \
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] $axi_crossbar_0
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# Create instance: axi_data_fifo_0, and set properties
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set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
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set_property -dict [ list \
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||||
CONFIG.DATA_WIDTH {512} \
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||||
CONFIG.READ_FIFO_DEPTH {512} \
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CONFIG.WRITE_FIFO_DEPTH {512} \
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] $axi_data_fifo_0
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# Create instance: axi_data_fifo_1, and set properties
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set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ]
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set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.READ_FIFO_DEPTH {512} \
|
||||
CONFIG.WRITE_FIFO_DEPTH {512} \
|
||||
] $axi_data_fifo_1
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||||
|
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# Create instance: axi_data_fifo_2, and set properties
|
||||
set axi_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.READ_FIFO_DEPTH {512} \
|
||||
CONFIG.WRITE_FIFO_DEPTH {512} \
|
||||
] $axi_data_fifo_2
|
||||
|
||||
# Create instance: axi_register_slice_0, and set properties
|
||||
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
] $axi_register_slice_0
|
||||
|
||||
# Create instance: axi_register_slice_1, and set properties
|
||||
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.ID_WIDTH {1} \
|
||||
] $axi_register_slice_1
|
||||
|
||||
# Create instance: axi_register_slice_2, and set properties
|
||||
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.ID_WIDTH {2} \
|
||||
] $axi_register_slice_2
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_crossbar_0/M00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_data_fifo_2_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_data_fifo_2/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_data_fifo_2/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
|
||||
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk]
|
||||
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn]
|
||||
connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_data_fifo_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_data_fifo_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
Reference in New Issue
Block a user